Plasma etch techniques for fabricating silicon structures from a substrate

• US 6,399,516 B1
• Filed: 10/29/1999
• Issued: 06/04/2002
• Est. Priority Date: 10/30/1998
• Status: Expired due to Fees

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Ayon, Arturo A.
• Primary Examiner(s): Mills, Gregory
• Assistant Examiner(s): Zervigon, Rudy
• Application Number:
  US09/430,565
• Time in Patent Office: 949 Days
• Field of Search: 216/2, 216/37, 280/735, 310/40.MM, 438/52, 438/739
• US Class Current: 438/739
• CPC Class Codes: B81C 1/0015 Cantilevers switches using MEMS H01H1/0036; electrostatic relays using micromechanics H01H59/0009; microelectro-mechanical resonators H03H9/02244
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 1/00936 Releasing the movable structure without liquid etchant
• CPC Class Codes: B81C 2201/0132 Dry etching, i.e. plasma etching, barrel etching, reactive ion etching [RIE], sputter etching or ion milling
• CPC Class Codes: B81C 2203/0778 Topology for facilitating the monolithic integration not provided for in B81C2203/0764 - B81C2203/0771
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/76251 using bonding techniques

Abstract

Provided is a method for producing a silicon element. A substrate configuration is provided that includes a silicon layer having a first face and a thickness corresponding to a specified thickness of the silicon element to be formed. The configuration includes a layer of an electrically-insulating material located below and adjacent to the silicon layer. A substantially vertical trench is etched from the first face in the silicon layer to a depth that exposes the insulating layer. Then the trench in the silicon layer is exposed to a gaseous environment that is reactive with silicon, to substantially lateral etch the silicon layer preferentially at the depth of the insulating layer along a surface of the insulating layer. This lateral etch is continued for a duration that results in release of a silicon element over the insulating layer. Also provided is a process for etching an angled trench in a silicon layer. Here, a substrate configuration is provided including a first silicon layer having at least one trench etched through the first silicon layer, and layer of an electrically-insulating material located below and adjacent to the silicon layer. The insulating layer includes an aperture that is located at a non-central location with respect to the trench and that corresponds to a prespecified trench angle. Included is a second silicon layer, in which the angled trench is to be formed, below and adjacent to the insulating layer. The trench in the first silicon layer is exposed to a gaseous environment that is reactive with silicon to etch that region of the second silicon layer that is exposed by the aperture in the insulating layer to a selected angled trench depth and prespecified trench angle.

Claims

1. A method for producing a silicon structure comprising the steps of:

providing a substrate configuration including a silicon layer having a first face and a thickness corresponding to a specified thickness of the silicon structure, and further including a layer of an electrically-insulating material located below and adjacent to the silicon layer;

etching a substantially vertical trench from the first face in the silicon layer to a depth that exposes the insulating layer; and

exposing the trench in the silicon layer to a gaseous environment that is reactive with silicon, to substantially lateral etch the silicon layer preferentially at the depth of the insulating layer along a surface of the insulating layer, the lateral etch being continued for a duration that results in release of a silicon element over the insulating layer.

2. The method of claim 1 wherein the electrically-insulating material comprises silicon dioxide.

3. The method of claim 1 wherein the electrically-insulating material comprises silicon nitride.

4. The method of claim 1 wherein the electrically-insulating material comprises a polymer.

5. The method of claim 1 wherein the step of providing a substrate configuration comprises:

forming the electrically-insulating layer on a first silicon substrate;

bonding a second silicon substrate to the formed insulating layer;

thinning the second silicon substrate to the specified silicon structure thickness.

6. The method of claim 5 wherein the step of forming the electrically-insulating layer comprises growing a layer of silicon dioxide.

7. The method of claim 5 wherein the step of forming the electrically-insulating layer comprises spin-coating a layer of polymer.

8. The method of claim 1 wherein the step of providing a substrate configuration comprises:

forming the electrically-insulating layer on a silicon substrate; and

forming on the insulating layer a polysilicon layer of the specified silicon structure thickness.

9. The method of claim 1 wherein the reactive gaseous environment comprises a plasma environment characterized as being an anisotropic silicon etchant.

10. The method of claim 9 wherein the reactive gaseous environment is provided as alternating time intervals of a first environment comprising SF₆ and a second environment comprising C₄F₈.

11. The method of claim 1 further comprising a step of photolithographically defining lateral edges of the silicon element, to be formed by the vertical trench etch in the silicon layer.

12. The method of claim 11 wherein the photolithographic definition of silicon structure lateral edges comprises photolithographic definition of a lateral anchor from the silicon structure to the silicon layer;

and wherein the step of reactive gaseous environment exposure of the silicon layer is carried out until the silicon structure is vertically suspended over the insulating layer but laterally anchored to the silicon layer.

13. The method of claim 11 wherein the photolithographic definition of silicon structure lateral edges comprises photolithographic definition of a trench that completely circumscribes the silicon element;

and wherein the step of reactive gaseous environment exposure of the silicon layer is carried out until the silicon element is completely released from the silicon layer.

14. The method of claim 1 further comprising the steps of:

fabricating electronics on the silicon layer;

coating the electronics with a removable protective coating, prior to the trench exposure to the reactive gaseous environment; and

removing the protective coating after production of the silicon structure.

15. The method of claim 1 further comprising a last step of coating the silicon structure with an electrically-insulating film.

16. The method of claim 1 further comprising the steps of:

etching a via from a back side of the substrate configuration through the insulating layer to expose the silicon layer; and

forming an electrically conducting layer in the via.

17. The method of claim 14 further comprising a last step of forming an electrical interconnection between the silicon structure and the electronics.

18. The method of claim 12 wherein the step of reactive gaseous environment exposure of the silicon layer is carried out until a doubly-supported silicon beam is suspended over the insulating layer.

19. The method of claim 12 wherein the step of reactive gaseous environment exposure of the silicon layer is carried out until a silicon cantilever beam is suspended over the insulating layer.

20. The method of claim 12 wherein the step of reactive gaseous environment exposure of the silicon layer is carried out until a pair of interdigitated finger elements are suspended over the insulating layer.

21. A method for etching an angled trench in a silicon layer comprising the steps of:

providing a substrate configuration including a first silicon layer having at least one trench etched through the first silicon layer a layer of an electrically-insulating material located below and adjacent to the silicon layer, the insulating layer including an aperture that is located at a non-central location with respect to the trench and corresponding to a prespecified trench angle, and further including a second silicon layer, in which the angled trench is to be formed, below and adjacent to the insulating layer; and

exposing the trench in the first silicon layer to a gaseous environment that is reactive with silicon to etch that region of the second silicon layer that is exposed by the aperture in the insulating layer to a selected angled trench depth and prespecified trench angle.

22. The method of claim 21 further comprising the step of removing the first silicon layer and the insulating layer after etching the angled trench in the second silicon layer.

23. The method of claim 21 wherein the electrically-insulating material comprises silicon dioxide.

24. The method of claim 21 wherein the electrically-insulating material comprises silicon nitride.

25. The method of claim 21 wherein the electrically-insulating material comprises a polymer.

26. The method of claim 21 wherein the step of providing a substrate configuration comprises:

forming the electrically-insulating layer on a first silicon substrate;

patterning the insulating layer to form an aperture in the insulating layer;

bonding a second silicon substrate to the formed insulating layer; and

etching at least one trench in the second silicon substrate.

27. The method of claim 26 wherein the step of forming the electrically-insulating layer comprises growing a layer of silicon dioxide.

28. The method of claim 26 wherein the step of forming the electrically-insulating layer comprises spin-coating a layer of polymer.

29. The method of claim 21 wherein the reactive gaseous environment comprises a plasma environment characterized as being an anisotropic silicon etchant.

30. The method of claim 29 wherein the reactive gaseous environment is provided as alternating time intervals of a first environment comprising SF₆ and a second environment comprising C₄F₈.