Technique to produce isolated junctions by forming an insulation layer

• US 6,399,973 B1
• Filed: 12/29/2000
• Issued: 06/04/2002
• Est. Priority Date: 12/29/2000
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Roberds, Brian
• Primary Examiner(s): Chaudhari, Chandra
• Assistant Examiner(s): Blum, David S
• Application Number:
  US09/752,335
• Publication Number:
  US 20020086510A1
• Time in Patent Office: 522 Days
• Field of Search: 438/197, 438/303, 257/288, 257/339
• US Class Current: 257/288
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled

Abstract

A method for isolating a source and a drain in an MOS transistor by forming an insulation layer adjacent to the source and an insulation layer adjacent to the drain, and an apparatus produced from such a method.

Claims

1. An apparatus comprising:

a semiconductor substrate;

a source region and a drain region formed by removing a portion of the semiconductor substrate adjacent to the gate stack;

an insulation layer formed on exposed portions of the semiconductor substrate within the source and drain regions; and

a source and a drain formed by depositing material in the source and drain regions.

2. The apparatus of claim 1, further comprising a first recess region and a second recess region formed by a vertical anisotropic etch, self-aligned with the gate stack, into in the semiconductor substrate, the area between the first and second recess regions defining a channel having a first sidewall and a second sidewall.

3. The apparatus of claim 2, further comprising a set of sidewall spacers formed adjacent to the channel to protect the first and second sidewalls of the channel.

4. The apparatus of claim 3, wherein the source and drain regions are formed by a vertical anisotropic etch into the semiconductor substrate aligned with the sidewall spacers.

5. The apparatus of claim 4, further comprising a source tip formed, after a removal of the sidewall spacers, adjacent to the first sidewall of the channel and a drain tip formed, after the removal of the sidewall spacers, adjacent to the second sidewall of the channel.

6. The apparatus of claim 5, wherein the source and drain have a graded dopant distribution.