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Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation region

  • US 6,399,978 B2
  • Filed: 12/11/2000
  • Issued: 06/04/2002
  • Est. Priority Date: 05/13/1999
  • Status: Expired due to Fees
First Claim
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1. An integrated circuit chip comprising:

  • a substrate;

    an opening in said substrate, said opening having at least one step;

    a first conductor in said opening below said step;

    a first diffusion region in said substrate adjacent said first conductor and below said step;

    a gate conductor over said step and in said opening;

    a second conductor over said substrate adjacent said gate conductor; and

    a second diffusion region in said substrate adjacent said second conductor.

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