Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation region

• US 6,399,978 B2
• Filed: 12/11/2000
• Issued: 06/04/2002
• Est. Priority Date: 05/13/1999
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies North America Corporation (Infineon Technologies AG), International Business Machines Corporation
• Original Assignee: Infineon Technologies North America Corporation (Infineon Technologies AG), International Business Machines Corporation
• Inventors: Radens, Carl J., Gruening, Ulrike
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Rao, Shrinivas H.
• Application Number:
  US09/733,038
• Publication Number:
  US 20020004290A1
• Time in Patent Office: 540 Days
• Field of Search: 257/301, 257/302, 257/303, 257/304, 257/306
• US Class Current: 257/301
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap

Abstract

A method and structure for manufacturing an integrated circuit chip includes a substrate and an opening in the substrate. The opening has at least one step and a first conductor in the opening below the step. The invention has a first diffusion region in the substrate adjacent the first conductor and below the step. A gate conductor is over the step and in the opening. A second conductor is over the substrate adjacent the gate conductor. A second diffusion region in the substrate is adjacent the second comductor.

Claims

1. An integrated circuit chip comprising:

a substrate;

an opening in said substrate, said opening having at least one step;

a first conductor in said opening below said step;

a first diffusion region in said substrate adjacent said first conductor and below said step;

a gate conductor over said step and in said opening;

a second conductor over said substrate adjacent said gate conductor; and

a second diffusion region in said substrate adjacent said second conductor.

2. The integrated circuit chip in claim 1, wherein said opening includes:

a lithographically formed gate opening;

a strap opening aligned with said gate opening using first spacers; and

an isolation opening aligned with said strap opening using second spacers.

3. The integrated circuit chip in claim 2, further comprising an isolation material filling said isolation opening, wherein said isolation material comprises a first portion of an active area isolation region, said integrated circuit chip further comprising active area stripes forming a second portion of said active area isolation region.

4. The integrated circuit chip in claim 2, wherein said first spacers and a portion of said second spacers are removed to form said step in said opening, wherein said second spacers comprise said first conductor.

5. The integrated circuit chip in claim 2, wherein said gate opening is wider than said strap opening and said strap opening is wider than said isolation opening.

6. The integrated circuit chip in claim 1, wherein a voltage in said gate conductor forms a conductive region in said substrate adjacent said step, said conductive region electrically connecting said first conductor and said second conductor.

7. The integrated circuit chip in claim 1, wherein said opening is formed over a deep trench capacitor, said first conductor bisecting a plane of said deep trench capacitor.

8. The integrated circuit chip in claim 1, wherein said first conductor comprises a source region, said second conductor comprises a drain region and said integrated circuit chip comprises a partially vertical transistor.