Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation region
First Claim
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1. An integrated circuit chip comprising:
- a substrate;
an opening in said substrate, said opening having at least one step;
a first conductor in said opening below said step;
a first diffusion region in said substrate adjacent said first conductor and below said step;
a gate conductor over said step and in said opening;
a second conductor over said substrate adjacent said gate conductor; and
a second diffusion region in said substrate adjacent said second conductor.
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Abstract
A method and structure for manufacturing an integrated circuit chip includes a substrate and an opening in the substrate. The opening has at least one step and a first conductor in the opening below the step. The invention has a first diffusion region in the substrate adjacent the first conductor and below the step. A gate conductor is over the step and in the opening. A second conductor is over the substrate adjacent the gate conductor. A second diffusion region in the substrate is adjacent the second comductor.
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Citations
8 Claims
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1. An integrated circuit chip comprising:
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a substrate;
an opening in said substrate, said opening having at least one step;
a first conductor in said opening below said step;
a first diffusion region in said substrate adjacent said first conductor and below said step;
a gate conductor over said step and in said opening;
a second conductor over said substrate adjacent said gate conductor; and
a second diffusion region in said substrate adjacent said second conductor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
a lithographically formed gate opening;
a strap opening aligned with said gate opening using first spacers; and
an isolation opening aligned with said strap opening using second spacers.
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3. The integrated circuit chip in claim 2, further comprising an isolation material filling said isolation opening, wherein said isolation material comprises a first portion of an active area isolation region, said integrated circuit chip further comprising active area stripes forming a second portion of said active area isolation region.
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4. The integrated circuit chip in claim 2, wherein said first spacers and a portion of said second spacers are removed to form said step in said opening, wherein said second spacers comprise said first conductor.
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5. The integrated circuit chip in claim 2, wherein said gate opening is wider than said strap opening and said strap opening is wider than said isolation opening.
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6. The integrated circuit chip in claim 1, wherein a voltage in said gate conductor forms a conductive region in said substrate adjacent said step, said conductive region electrically connecting said first conductor and said second conductor.
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7. The integrated circuit chip in claim 1, wherein said opening is formed over a deep trench capacitor, said first conductor bisecting a plane of said deep trench capacitor.
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8. The integrated circuit chip in claim 1, wherein said first conductor comprises a source region, said second conductor comprises a drain region and said integrated circuit chip comprises a partially vertical transistor.
Specification