Semiconductor integrated circuit

• US 6,399,991 B1
• Filed: 11/13/2000
• Issued: 06/04/2002
• Est. Priority Date: 11/19/1999
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Ando, Yasuhiro
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Menz, Douglas M
• Application Number:
  US09/709,631
• Time in Patent Office: 568 Days
• Field of Search: 257/355, 257/358, 257/360, 257/401, 257/313, 257/291, 357/41, 357/45
• US Class Current: 257/355
• CPC Class Codes: H01L 21/765 by field effect H01L21/76264 takes precedence

Abstract

In the guard ring section, four regions, p⁺ diffusion region, n⁺ diffusion region, n⁺ diffusion region, and p⁺ diffusion region, are formed to surround a hard macro and disposed in the order of this from the inside, and the inside two regions are disposed in an n well, and the outside two regions are disposed in a p well. A potential VSS is applied in the innermost p⁺ diffusion region and the outermost p⁺ diffusion region, and a potential VDD is applied in the two n⁺ diffusion regions disposed between these p⁺ diffusion regions. As a result, capacitors are formed between the n well and the p⁺ diffusion region formed in the n well, and between the p well and the n⁺ diffusion region formed in the p well, and therefore noise from outside is shielded, power source noise is absorbed, and malfunctions of the macro cell are prevented.

Claims

1. A semiconductor integrated circuit comprising:

a macro cell formed on a semiconductor substrate, and

a guard ring provided to surround the circumference of said macro cell, said guard ring comprising;

an n well disposed so as to surround the macro cell,

a p well disposed adjacent to said n well to surround the macro cell,

a first n⁺ diffusion region disposed in the surface layer of the n well to surround the macro cell in which a first potential is applied,

a second n⁺ diffusion region disposed in the surface layer of the p well to surround the macro cell in which the first potential is applied,

a first p⁺ diffusion region disposed in the surface layer of the n well to surround the macro cell in which a second potential lower than the first potential is applied, and

a second p⁺ diffusion region disposed in the surface layer of the p well to surround the macro cell in which the second potential is applied.

2. The semiconductor integrated circuit according to claim 1, further comprising:

a first wiring connected to both of said first and second n⁺ diffusion regions to apply the first potential to said first and second n⁺ diffusion regions,

wherein said first and second n⁺ diffusion regions are disposed beneath the first wiring and parallel to the first wiring.

3. The semiconductor integrated circuit according to claim 1, further comprising:

a second wiring connected to said first p⁺ diffusion region to apply the second potential to said first p⁺ diffusion region, and

a third wiring connected to both of said second wiring and said second p⁺ diffusion region to apply the second potential to said second p⁺ diffusion region,

wherein said first and second p⁺ diffusion regions are disposed beneath the second and third wirings respectively and parallel to the second and third wirings.

4. The semiconductor integrated circuit according to claim 1, further comprising:

a first wiring connected to both of said first and second p⁺ diffusion regions to apply the second potential to said first and second p⁺ diffusion regions,

wherein said first and second p⁺ diffusion regions are disposed beneath the first wiring and parallel to the first wiring.

5. The semiconductor integrated circuit according to claim 1, further comprising:

a second wiring connected to said first n⁺ diffusion region to apply the first potential to said first n⁺ diffusion region, and

a third wiring connected to both of said second wiring and said second n⁺ diffusion region to apply the first potential to said second n⁺ diffusion region,

wherein said first and second n⁺ diffusion regions are disposed beneath the second and third wirings respectively and parallel to the second and third wirings.

6. The semiconductor integrated circuit according to claim 1, wherein said macro cell is a hard macro.

7. The semiconductor integrated circuit according to claim 1, wherein said macro cell is a buffer.

8. A semiconductor integrated circuit comprising:

a macro cell formed on a semiconductor substrate, and

a guard ring provided to surround the circumference of said macro cell, said guard ring comprising;

an n well disposed so as to surround the macro cell,

a p well disposed adjacent to said n well to surround the macro cell,

a first n⁺ diffusion region disposed in the surface layer of the n well to surround the macro cell in which a first potential is applied,

a second n⁺ diffusion region disposed in the surface layer of the p well to surround the macro cell in which the first potential is applied, and

a first p⁺ diffusion region disposed in the surface layer of the p well to surround the macro cell in which a second potential lower than the first potential is applied.

9. The semiconductor integrated circuit according to claim 8, further comprising:

a first wiring connected to both of said first and second n⁺ diffusion regions to apply the first potential to said first and second n⁺ diffusion regions,

wherein said first and second n⁺ diffusion regions are disposed beneath the first wiring and parallel to the first wiring.

10. A semiconductor integrated circuit comprising:

a macro cell formed on a semiconductor substrate, and

a guard ring provided to surround the circumference of said macro cell, said guard ring comprising;

an n well disposed so as to surround the macro cell,

a p well disposed adjacent to said n well to surround the macro cell,

a first n⁺ diffusion region disposed in the surface layer of the n well to surround the macro cell in which a first potential is applied,

a first p⁺ diffusion region disposed in the surface layer of the n well to surround the macro cell in which a second potential lower than the first potential is applied, and

a second p⁺ diffusion region disposed in the surface layer of the p well to surround the macro cell in which the second potential is applied.