Semiconductor integrated circuit
First Claim
1. A semiconductor integrated circuit comprising:
- a macro cell formed on a semiconductor substrate, and a guard ring provided to surround the circumference of said macro cell, said guard ring comprising;
an n well disposed so as to surround the macro cell, a p well disposed adjacent to said n well to surround the macro cell, a first n+ diffusion region disposed in the surface layer of the n well to surround the macro cell in which a first potential is applied, a second n+ diffusion region disposed in the surface layer of the p well to surround the macro cell in which the first potential is applied, a first p+ diffusion region disposed in the surface layer of the n well to surround the macro cell in which a second potential lower than the first potential is applied, and a second p+ diffusion region disposed in the surface layer of the p well to surround the macro cell in which the second potential is applied.
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Accused Products
Abstract
In the guard ring section, four regions, p+ diffusion region, n+ diffusion region, n+ diffusion region, and p+ diffusion region, are formed to surround a hard macro and disposed in the order of this from the inside, and the inside two regions are disposed in an n well, and the outside two regions are disposed in a p well. A potential VSS is applied in the innermost p+ diffusion region and the outermost p+ diffusion region, and a potential VDD is applied in the two n+ diffusion regions disposed between these p+ diffusion regions. As a result, capacitors are formed between the n well and the p+ diffusion region formed in the n well, and between the p well and the n+ diffusion region formed in the p well, and therefore noise from outside is shielded, power source noise is absorbed, and malfunctions of the macro cell are prevented.
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Citations
10 Claims
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1. A semiconductor integrated circuit comprising:
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a macro cell formed on a semiconductor substrate, and a guard ring provided to surround the circumference of said macro cell, said guard ring comprising;
an n well disposed so as to surround the macro cell, a p well disposed adjacent to said n well to surround the macro cell, a first n+ diffusion region disposed in the surface layer of the n well to surround the macro cell in which a first potential is applied, a second n+ diffusion region disposed in the surface layer of the p well to surround the macro cell in which the first potential is applied, a first p+ diffusion region disposed in the surface layer of the n well to surround the macro cell in which a second potential lower than the first potential is applied, and a second p+ diffusion region disposed in the surface layer of the p well to surround the macro cell in which the second potential is applied. - View Dependent Claims (2, 3, 4, 5, 6, 7)
a first wiring connected to both of said first and second n+ diffusion regions to apply the first potential to said first and second n+ diffusion regions, wherein said first and second n+ diffusion regions are disposed beneath the first wiring and parallel to the first wiring.
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3. The semiconductor integrated circuit according to claim 1, further comprising:
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a second wiring connected to said first p+ diffusion region to apply the second potential to said first p+ diffusion region, and a third wiring connected to both of said second wiring and said second p+ diffusion region to apply the second potential to said second p+ diffusion region, wherein said first and second p+ diffusion regions are disposed beneath the second and third wirings respectively and parallel to the second and third wirings.
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4. The semiconductor integrated circuit according to claim 1, further comprising:
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a first wiring connected to both of said first and second p+ diffusion regions to apply the second potential to said first and second p+ diffusion regions, wherein said first and second p+ diffusion regions are disposed beneath the first wiring and parallel to the first wiring.
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5. The semiconductor integrated circuit according to claim 1, further comprising:
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a second wiring connected to said first n+ diffusion region to apply the first potential to said first n+ diffusion region, and a third wiring connected to both of said second wiring and said second n+ diffusion region to apply the first potential to said second n+ diffusion region, wherein said first and second n+ diffusion regions are disposed beneath the second and third wirings respectively and parallel to the second and third wirings.
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6. The semiconductor integrated circuit according to claim 1, wherein said macro cell is a hard macro.
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7. The semiconductor integrated circuit according to claim 1, wherein said macro cell is a buffer.
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8. A semiconductor integrated circuit comprising:
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a macro cell formed on a semiconductor substrate, and a guard ring provided to surround the circumference of said macro cell, said guard ring comprising;
an n well disposed so as to surround the macro cell, a p well disposed adjacent to said n well to surround the macro cell, a first n+ diffusion region disposed in the surface layer of the n well to surround the macro cell in which a first potential is applied, a second n+ diffusion region disposed in the surface layer of the p well to surround the macro cell in which the first potential is applied, and a first p+ diffusion region disposed in the surface layer of the p well to surround the macro cell in which a second potential lower than the first potential is applied. - View Dependent Claims (9)
a first wiring connected to both of said first and second n+ diffusion regions to apply the first potential to said first and second n+ diffusion regions, wherein said first and second n+ diffusion regions are disposed beneath the first wiring and parallel to the first wiring.
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10. A semiconductor integrated circuit comprising:
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a macro cell formed on a semiconductor substrate, and a guard ring provided to surround the circumference of said macro cell, said guard ring comprising;
an n well disposed so as to surround the macro cell, a p well disposed adjacent to said n well to surround the macro cell, a first n+ diffusion region disposed in the surface layer of the n well to surround the macro cell in which a first potential is applied, a first p+ diffusion region disposed in the surface layer of the n well to surround the macro cell in which a second potential lower than the first potential is applied, and a second p+ diffusion region disposed in the surface layer of the p well to surround the macro cell in which the second potential is applied.
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Specification