Semiconductor device having damascene interconnection structure that prevents void formation between interconnections

• US 6,400,031 B1
• Filed: 06/10/1999
• Issued: 06/04/2002
• Est. Priority Date: 06/11/1998
• Status: Expired due to Term

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Harada, Yusuke
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Peralta, Ginette
• Application Number:
  US09/329,249
• Publication Number:
  US 20020036346A1
• Time in Patent Office: 1,090 Days
• Field of Search: 257/741, 257/751, 257/758, 257/762, 257/767, 257/776, 257/748, 257/752, 257/763, 257/764, 257/770, 257/774, 257/775, 438/927, 438/627, 438/643, 438/653, 438/622, 438/629
• US Class Current: 257/776
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device is made up of a first insulating layer having a through hole; a first interconnection which comprises a first conductive layer, a first barrier layer, and a first main interconnection, and a second interconnection connected to one of the first conductive layer and the first barrier layer. Accordingly, the semiconductor device can avoid a problem so that the Cu of the first main interconnection transfers from a portion connected to the second interconnection due to cause electromigration, the connected portion becomes a void, and the first interconnection is disconnected to the second interconnection.

Claims

1. A semiconductor device comprising:

a first insulating layer;

a first interconnection formed in a first groove within the first insulating layer, the first interconnection having a first conductive layer formed in the first groove, a first barrier layer formed on the first conductive layer, and a first main interconnection formed on the first barrier layer, the first inerconnection having a concave portion therein;

a second insulating layer formed on the first insulating layer; and

a second interconnection formed in a second groove within the second insulating layer, the second interconnection having a convex portion that extends into the concave portion of the first interconnection,

the first interconnection being electrically connected to the second interconnection by the convex portion that extends into the concave portion.

2. The semiconductor device of claim 1, wherein the first groove has a longitudinal direction corresponding to a flow of electrons.

3. The semiconductor device of claim 1, wherein the first barrier layer comprises TiN and the first conductive layer comprises one of a barrier metal and a silicide compound.

4. The semiconductor device of claim 1, wherein the second interconnection has a second conductive layer formed on the second insulating layer within the second groove, a second barrier layer formed on the second conductive layer, and a second main interconnection formed on the second barrier layer and filling the second groove, the convex portion of the second interconnection extending into the concave portion of the first interconnection so that the second conductive layer contacts a sidewall of the first interconnection.

5. The semiconductor device of claim 4, wherein the first and second main interconnections are Cu.

6. The semiconductor device of claim 1, wherein the first and second interconnections have a damascene structure.

7. A semiconductor device comprising:

a first insulating layer;

a first interconnection formed in a first groove within the first insulating layer, the first interconnection having a first conductive layer formed on the first insulating layer within the first groove, a first barrier layer formed on the first conductive layer, and a first main interconnection formed on the first barrier layer and filling the first groove;

a second insulating layer formed on the first insulating layer; and

a second interconnection formed in a second groove within the second insulating layer, the second interconnection extending from an upper surface of the first interconnection into the first insulating layer to sidewalls of the first conductive layer on first and second sides of the first interconnection.

8. The semiconductor device of claim 7, wherein the first groove has a longitudinal direction corresponding to a flow of electrons.

9. The semiconductor device of claim 7, wherein the first barrier layer comprises TiN and the first conductive layer comprises one of a barrier metal and a silicide compound.

10. The semiconductor device of claim 7, wherein the second interconnection includes a second conductive layer formed on the second insulating layer within the second groove, a second barrier layer formed on the second conductive layer, and a second main interconnection formed on the second barrier layer and filling the second groove, the second interconnection extending into the first insulating layer so that the second conductive layer contacts the sidewalls of the first interconnection.

11. The semiconductor device of claim 10, wherein the first and second main interconnections are Cu.

12. The semiconductor device of claim 7, wherein the first and second interconnections have a damascene structure.

13. The semiconductor device of claim 7, wherein the first groove is formed as a concave portion in the first insulating layer.