Test system and manufacturing of semiconductor device

• US 6,400,173 B1
• Filed: 10/20/2000
• Issued: 06/04/2002
• Est. Priority Date: 11/19/1999
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Sato, Masayuki, Shimizu, Isao, Fukiage, Hiroshi
• Primary Examiner(s): Le, N.
• Assistant Examiner(s): Kerveros, James
• Application Number:
  US09/692,468
• Time in Patent Office: 592 Days
• Field of Search: 324/765, 324/754, 324/755, 324/158.1, 324/758, 324/757, 324/760, 324/761
• US Class Current: 324/754.07
• CPC Class Codes: G01R 31/2806 Apparatus therefor, e.g. test stations, drivers, analysers, conveyors G01R31/2805, G01R31/281, G01R31/2818 take precedence
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/31917 Stimuli generation or application of test patterns to the device under test [DUT]
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/30105 Capacitance
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A test circuit is provided on a probe card or a wafer on which semiconductor chips to be tested are formed. The test circuit and each of the semiconductor chips to be tested are electrically connected to each other to perform testing, whereby the test can be carried out without using a tester. Conducting a test in such a wafer stage within an aging device allows the simplification or omission of a test subsequent to packaging.

Claims

1. A test system which performs electrical tests on semiconductor chips formed on a semiconductor wafer, comprising:

a probe card which is provided with conductive needles in alignment with the placement of electrode pads in the semiconductor chips and connected to a plurality of test circuits, each of said test circuits being placed on said probe card, and arranged to provide test input signals to said semiconductor chips and receive output signals from said semiconductor chips to generate a test result based on a program; and

a control device which writes said program in said test circuit and stores therein said test result outputted from said test circuit.

2. The test system according to claim 1, wherein said test circuit includes an FPGA or a microcomputer device.

3. A test system according to claim 1, wherein the test circuits are test chips mounted on the probe card.

4. A test system according to claim 1, wherein the probe card comprises a frame and a semiconductor substrate in which the plurality of test circuits are formed.

5. A test system according to claim 4, wherein the conductive needles are formed on a surface of the semiconductor substrate.

6. A test system which conducts electrical tests on semiconductor chips formed on a semiconductor wafer, comprising:

a test circuit, which provides test input signals to said semiconductor chips and receives output signals from said semiconductor chips to generate a test result, formed on said semiconductor wafer,

a probing module having test wirings formed therein, which connect the semiconductor chips and said test circuit; and

a power supply device which supplies power to said each semiconductor chip and said test circuit through said probing module.

7. The test system according to claim 6, wherein said test circuit includes an FPGA or a microcomputer device.

8. The test system according to claim 7, wherein said test circuit conducts tests on a plurality of semiconductor chips formed on a semiconductor wafer.

9. A test system according to claim 6, wherein the test circuit is surrounded by a plurality of said semiconductor chips to be tested.

10. A test system which performs electrical tests on semiconductor chips formed on a semiconductor wafer, comprising:

a test circuit which provides test input signals to said semiconductor chips and receives output signals from said semiconductor chips to generate a test a result, wherein said test circuit is formed in a scribe area or a chip area in the semiconductor wafer; and

test wirings which are formed in the scribe area or a test wiring layer in the semiconductor wafer and connect said test circuit to the semiconductor chips.

11. The test system according to claim 10, wherein said test circuit includes an FPGA or a microcomputer device.

12. The test system according to claim 11, wherein said test circuit conducts tests on a plurality of semiconductor chips formed on a semiconductor wafer.