Semiconductor integrated circuit, liquid crystal apparatus, electronic apparatus and method for testing semiconductor integrated circuit

• US 6,400,196 B1
• Filed: 07/21/2000
• Issued: 06/04/2002
• Est. Priority Date: 07/23/1999
• Status: Expired due to Term

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Kamijo, Haruo, Aoki, Shigeki
• Primary Examiner(s): Le, Dinh T.
• Application Number:
  US09/620,861
• Time in Patent Office: 683 Days
• Field of Search: 327/141, 327/143, 327/198, 365/233, 365/201
• US Class Current: 327/143
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/3187 Built-in tests

Abstract

A semiconductor integrated circuit has a reset signal generation circuit (10) that generates a reset signal (12) having a reset period based on a power-on reset signal (11), and a latch circuit (20) having an initialization circuit (23) that initializes a latch output (21) based on the reset signal (12). The reset signal generation circuit (10) has a delay circuit (14) that can variably set a pulse width corresponding to the reset period of the reset signal (12). An output line of the delay circuit (14) is connected to a first pad terminal (32). An output line of the initialization circuit (23) is connected to a second pad terminal (34). When the semiconductor integrated circuit is verified, the first and second pad terminals (32, 34) are brought in contact with a probe (40). During this verification process, according to input/output loads of a tester that is connected to the first pad terminal (32), the pulse width of the reset signal (12) is set wider than that during the normal use when the pad terminals are not contacted with a probe.

Claims

1. A semiconductor integrated circuit having a power input means for receiving power when power is turned on, said semiconductor integrated circuit comprising:

a reset signal generation circuit that generates a reset signal having a reset pulse width in response to an input signal that is inputted at least immediately after power is turned on;

at least one latch circuit having an initialization circuit that initializes a latch output based on the reset signal;

a first pad terminal that is connected to the reset signal generation circuit; and

at least one second pad terminal that is connected to an output line of the initialization circuit, wherein

the reset signal generation circuit has a delay circuit that variably sets the reset pulse width of the reset signal according to a load that is connected to the first pad terminal.

2. A semiconductor integrated circuit according to claim 1, wherein the first pad terminal is connected to an output line of the delay circuit.

3. A semiconductor integrated circuit according to claim 1, wherein the first pad terminal is connected to an input line of the delay circuit.

4. A semiconductor integrated circuit according to claim 1, further comprising a fuse element that is connected to an output line of the initialization circuit, wherein the logic level of the latch output is dependent on whether said fuse element is in an open state or in a closed state.

5. A semiconductor integrated circuit according to claim 1, wherein:

the reset signal generation circuit includes a plurality of sub-circuits having respective output nodes each with a respective output impedance, said first pad terminal being coupled to the output node of at least a selected one of said sub-circuits such that the output impedance of the selected sub-circuit and the impedance said first pad terminal combined to establish a first slew rate for the rise and fall times of the selected sub-circuit'"'"'s output node; and

the impedance of the output line of the initialization circuit and the impedance of the second pad terminal combined to establish a second slew rate for the rise and fall times of said output line, said first slew rate being lower than said second slew rate.

6. A semiconductor integrated circuit according to claim 1, wherein the reset signal generation circuit includes a one-shot pulse generation circuit that generates a one-shot reset signal having a pulse width corresponding to the reset pulse width of the reset signal and formed by the delay circuit delaying the input signal.

7. A semiconductor integrated circuit according to claim 1, wherein

the reset signal generation circuit further includes:

a one-shot pulse generation circuit that generates a one-shot pulse based on the input signal; and

a pulse width variable circuit that includes the delay circuit and changes the pulse width of the one-shot pulse according to a load that is connected to the first pad terminal.

8. A semiconductor integrated circuit according to claim 1, wherein the input signal applied to the reset signal generation circuit alternates logic levels a plurality of times during a period from a time immediately after the power is turned on to a time when the power is turned off.

9. A semiconductor integrated circuit according to claim 1, further comprising a reference frequency generation circuit that generates a reference frequency based on the latch output.

10. A semiconductor integrated circuit according to claim 9, wherein an output frequency of the reference frequency generation circuit is used as an alternating signal that alternately drives a liquid crystal.

11. A semiconductor integrated circuit device comprising:

a semiconductor integrated circuit having a power input means for receiving power when power is turned on, said semiconductor integrated circuit including;

a reset signal generation circuit that generates a reset signal having a reset pulse width in response to an input signal that is inputted at least immediately after power is turned on, wherein said input signal alternates logic levels a plurality of times during a period from a time immediately after the power is turned on to a time when the power is turned off;

at least one latch circuit having an initialization circuit that initializes a latch output based on the reset signal;

a first pad terminal that is connected to the reset signal generation circuit; and

at least one second pad terminal that is connected to an output line of the initialization circuit, wherein

the reset signal generation circuit has a delay circuit that variably sets the reset pulse width of the reset signal according to a load that is connected to the first pad terminal; and

an OR gate that takes the logical sum of a power-on signal and a predetermined signal for controlling initialization of said latch circuit, wherein the output of said OR gate is said input signal that is provided to said reset signal generation circuit.

12. A semiconductor integrated circuit device comprising:

a semiconductor integrated circuit having a power input means for receiving power when power is turned on, said semiconductor integrated circuit including;

a reset signal generation circuit that generates a reset signal having a reset pulse width in response to an input signal that is inputted at least-immediately after power is turned on;

at least one latch circuit having an initialization circuit that initializes a latch output based on the reset signal;

a first pad terminal that is connected to the reset signal generation circuit; and

at least one second pad terminal that is connected to an output line of the initialization circuit, wherein

the reset signal generation circuit has a delay circuit that variably sets the reset pulse width of the reset signal according to a load that is connected to the first pad terminal; and

a reference voltage generation circuit that generates a reference voltage based on the latch output.

13. A semiconductor integrated circuit device according to claim 12, further comprising a liquid crystal driving voltage generation circuit that generates a liquid crystal driving voltage in a plurality of levels based on, an output voltage from the reference voltage generation circuit.

14. A liquid crystal apparatus comprising:

a liquid crystal driver IC having a power input means for receiving power when power is turned on, said liquid crystal driver IC being formed from a semiconductor integrated circuit including;

a reset signal generation circuit for generating a reset signal having a reset pulse width in response to an input signal that applied at least immediately after power is turned on;

at least one latch circuit having an initialization circuit for initializing a latch output in response to said reset signal;

a first pad terminal coupled to said reset signal generation circuit; and

at least one second pad terminal coupled to an output line of said initialization circuit, wherein said reset signal generation circuit includes a delay circuit that variably sets the reset pulse width of said reset signal according to a load applied to said first pad terminal; and

a liquid crystal panel that is driven by the liquid crystal driver IC.

15. An electronic apparatus comprising:

a liquid crystal apparatus having a power input means for receiving power when power is turned on, said liquid crystal driver IC being formed from a semiconductor integrated circuit including;

a reset signal generation circuit for generating a reset signal having a reset pulse width in response to an input signal that applied at least immediately after power is turned on;

at least one latch circuit having an initialization circuit for initializing a latch output in response to said reset signal;

a first pad terminal coupled to said reset signal generation circuit; and

at least one second pad terminal coupled to an output line of said initialization circuit, wherein said reset signal generation circuit includes a delay circuit that variably sets the reset pulse width of said reset signal according to a load applied to said first pad terminal; and

a liquid crystal panel that is driven by the liquid crystal driver IC.

16. A method for testing a semiconductor integrated circuit, the method comprising:

a first step of contacting a probe to a first pad terminal coupled to a delay circuit of the semiconductor integrated circuit, wherein said delay circuit produces a first delay time when no probe is in contact with said first pad and a producing a second delay time when said probe is in contact with said first pad, said second delay time being greater than said first delay time;

a second step of generating, by a reset signal generation circuit in the semiconductor integrated circuit, a reset signal having a pulse width dependent on the delay time produced by said delay circuit;

a third step of initializing a latch output, in at least one latch circuit having an initializing circuit, by the initializing circuit based on the reset signal; and

a fourth step of monitoring an output voltage of the initialization circuit by means of a second pad terminal.

17. A method for testing a semiconductor integrated circuit according to claim 16, further comprising:

a fifth step of monitoring a reference signal that is set based on an initialized latch output; and

a sixth step of cutting a fuse element that is connected to an output line of the initialization circuit based on a monitoring result conducted in the fifth step.

18. A method for testing a semiconductor integrated circuit according to claim 17, further comprising, after the sixth step, a seventh step of monitoring through the second pad terminal an output of the initialization circuit that is modified by the cut fuse element.

19. A method for testing a semiconductor integrated circuit according to claim 17, wherein the reference signal that is monitored in the fifth step has a reference voltage for generating liquid crystal driving voltages in a plurality of levels.

20. A method for testing a semiconductor integrated circuit according to claim 17 wherein, the reference signal that is monitored in the fifth step is an alternating signal for alternately driving the liquid crystal.

21. A semiconductor integrated circuit having a test operation mode and a normal operation mode, said semiconductor integrated circuit comprising:

a reset input node for receiving a reset signal;

a reset signal generation circuit for generating a reset pulse signal in response to said reset signal, said reset pulse signal having a first pulse width when said semiconductor circuit is in said test operation mode and having a second pulse width when said semiconductor circuit is in said normal operation mode, said first pulse width being longer than said second pulse width;

a latch circuit coupled to receive said reset pulse signal and having an output latch node, said latch further having a an intermediate node selectively coupled to a power rail through a fuse, said latch being effective for latching the logic value of said reset pulse signal and outputting the latched value on said output latch node when said fuse is blown, and being effective for ignoring said reset pulse signal and maintaining the logic value of said output latch node constant when said fuse is not blown.

22. The semiconductor integrated circuit of claim 21, wherein when said fuse is blown, said latch is characterized by a latch response time for latching the logic level of said reset pulse signal, said latch response time having a first time span when said semiconductor integrated circuit is in said test operation mode and having a second time span when said semiconductor circuit is in said normal operation mode, said first time span being longer than said second time span.

23. The semiconductor integrated circuit of claim 22, further having a first probe pad coupled to said intermediate node for receiving a test probe when said semiconductor integrated circuit is in said test operation mode, said test probe having a first capacitive load effective for setting said first time span of said latch response time.

24. The semiconductor integrated circuit of claim 23, further having a second probe pad coupled to said reset signal generation circuit for adjusting the length of said first pulse width of said reset pulse signal to assure that said first pulse width is greater than said first time span of said latch response time.

25. The semiconductor integrated circuit of claim 24, wherein said second probe pad has a predetermined load for creating a specific time constant sufficient for producing said first pulse width.