Switch circuit with back gate voltage control and series regulator

• US 6,400,209 B1
• Filed: 03/16/2000
• Issued: 06/04/2002
• Est. Priority Date: 08/05/1999
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Inatomi, Koichi, Matsuyama, Toshiyuki
• Primary Examiner(s): Cunningham, Terry D.
• Assistant Examiner(s): ENGLUND, TERRY LEE
• Application Number:
  US09/526,748
• Time in Patent Office: 810 Days
• Field of Search: 323/282, 327/534, 327/365, 327/427, 327/538, 327/543, 327/434, 327/537
• US Class Current: 327/534
• CPC Class Codes: G05F 1/565 sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor G05F1/563 takes precedence
• CPC Class Codes: H02J 7/0031 using battery or load disconnect circuits H02J9/002 takes precedence
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A switch circuit has an input terminal and an output terminal and when turned on, provides a voltage at its input terminal to its output terminal. A transistor is connected between the input and output terminals. A gate drive circuit is connected to the gate of the transistor and provides a gate drive signal to the gate. The gate drive circuit, in response to a first control signal, causes the gate drive signal to have one of a first voltage derived from an input voltage at the input terminal and a low potential voltage. A back gate drive circuit is connected to a back gate of the transistor and provides a back gate drive signal to the back gate. The back gate drive signal controls a voltage applied to the back gate of the transistor depending on whether the transistor is turned on or off. The switch circuit may be used to selectively supply battery power to a portable electronic device.

Claims

1. A switch circuit including an input terminal and an output terminal, the switch circuit comprising:

a MOS transistor connected between the input and output terminals;

a gate drive circuit connected to a gate of the transistor to provide a gate drive signal thereto, wherein the gate drive circuit responds to a first control signal provided to the switch circuit and causes the gate drive signal to have one of a first drive voltage, which is derived from a voltage at the input terminal, and a low potential power supply level; and

a back gate drive circuit connected to a back gate of the transistor for providing a back gate drive signal thereto having substantially the same phase as the gate drive signal, wherein the back gate drive circuit controls a voltage of the back gate drive signal in accordance with whether the transistor is activated or deactivated.

2. The switch circuit according to claim 1, wherein the back gate drive circuit responds to the first control signal and causes the back gate drive signal to have substantially the same voltage as the gate drive signal when the transistor is deactivated, and substantially the same voltage as the output terminal when the transistor is activated.

3. The switch circuit according to claim 1, wherein the gate drive circuit includes a charge pump circuit connected to the input terminal, wherein the charge pump circuit is activated by the first control signal and pulls up the voltage at the input terminal to generate the first drive voltage.

4. The switch circuit according to claim 1, further comprising a level shift circuit for shifting a voltage level of the first control signal to generate a second control signal, wherein the level shift circuit provides the second control signal to at least one of the gate drive circuit and the back gate drive circuit, and wherein whichever of the gate drive circuit and the back gate drive circuit receiving the second control signal controls the voltages of the gate drive signal and the back gate drive signal in response to the second control signal, respectively.

5. A series regulator including an input terminal and an output terminal, the series regulator comprising:

a switch circuit including,

a MOS transistor connected between the input and output terminals;

a gate drive circuit connected to a gate of the transistor to provide a gate drive signal thereto, wherein the gate drive circuit responds to a first control signal and to a detection signal provided to the switch circuit and causes the gate drive signal to have one of a first drive voltage, which is derived from a voltage at the input terminal, and a low potential power supply level; and

a back gate drive circuit connected to a back gate of the transistor for providing a back gate drive signal thereto having substantially the same phase as the gate drive signal, wherein the back gate drive circuit controls a voltage of the back gate drive signal in accordance with whether the transistor is activated or deactivated; and

a comparison amplifier for comparing the voltage at the output terminal with a predetermined reference voltage to generate the detection signal based on the comparison result.

6. The series regulator according to claim 5, wherein the back gate drive circuit responds to the first control signal and causes the back gate drive signal to have substantially the same voltage as the gate drive signal when the transistor is deactivated, and substantially the same voltage as the output terminal when the transistor is activated.

7. The series regulator according to claim 5, wherein the gate drive circuit includes a charge pump circuit connected to the input terminal, wherein the charge pump circuit is activated by the first control signal and pulls up the voltage at the input terminal to generate the first drive voltage.

8. The series regulator according to claim 5, further comprising a level shift circuit for shifting a voltage level of the first control signal to generate a second control signal, wherein the level shift circuit provides the second control signal to at least one of the gate drive circuit and the back gate drive circuit, and wherein whichever of the gate drive circuit and the back gate drive circuit receiving the second control signal controls the voltages of the gate drive signal and the back gate drive signal in response to the second control signal, respectively.

9. A switch circuit having an input terminal and an output terminal, comprising:

a main switch connected between the input terminal and the output terminal;

a charge pump connected to the input terminal and the main switch and receiving a first control signal, the first control signal activating and deactivating the charge pump;

a driver circuit connected to the charge pump and the main switch and receiving the first control signal, wherein when the first control signal is activated, the charge pump pulls up an input voltage supplied to the input terminal to a predetermined level and provides a drive voltage to the driver circuit, which in turn generates a drive signal having substantially the same voltage as the drive voltage, wherein the driver circuit supplies the drive signal to the main switch, thereby activating the main switch such that the input voltage is supplied at the output terminal, and wherein when the first control signal is deactivated, the drive signal is deactivated, which deactivates the main switch such that the input voltage is not provided at the output terminal;

a level shift circuit that receives the first control signal and generates a second control signal having substantially the same voltage level as the input voltage; and

a back gate drive circuit connected between the level shift circuit and the main switch and, in response to receiving the second control signal, the back gate drive circuit generates a back gate drive signal having substantially the same voltage as the voltage at the output terminal to the main switch, wherein the back gate drive circuit comprises;

first and second transistors connected in series between the output terminal and a ground, and the gates of the first and second transistors are connected together, wherein the second control signal is provided to a node between the gates of the first and second transistors and the back gate drive signal is generated at a node between the drains of the first and second transistors.

10. The switch circuit of claim 9, wherein the main switch comprises an NMOS transistor, wherein the drain of the transistor is connected to the input terminal, the source of the transistor is connected to the output terminal, the gate of the transistor is connected to the driver circuit, and a back gate of the transistor is connected to the back gate drive circuit.

11. The switch circuit of claim 10, further comprising:

a driven circuit connected to the output terminal of the switch circuit, wherein the switch circuit supplies power to the driven circuit when the transistor is turned on.