Electronically-eraseable programmable read-only memory having reduced-page-size program and erase

• US 6,400,603 B1
• Filed: 05/03/2000
• Issued: 06/04/2002
• Est. Priority Date: 05/03/2000
• Status: Expired due to Term

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Advanced Technology Materials, Inc. (Entegris Incorporated)
• Inventors: Barnett, Philip C., Allum, Dean, Sowards, David, Blyth, Trevor
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US09/564,324
• Time in Patent Office: 762 Days
• Field of Search: 365/185.12, 365/185.11, 365/185.33, 365/104
• US Class Current: 365/185.12
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits

Abstract

By reducing the size of the blocks or pages that are contained in a FLASH EEPROM array that must be erased in a write or erase operation, the size of register needed is reduced, making it easier for the processor to handle smaller blocks of information, reducing the size and complexity of the microprocessor, and increasing the endurance of the FLASH EEPROM allowing it to be used in place of the state of the art EEPROM. Replacing mask ROM by flash EEPROM allows full testing of the code storage area as well as allowing customers to use that space for testing in their manufacturing procedures. The code used for testing can then be cleared and reprogrammed with the final code storage before final shipment.

Claims

1. An array of non-volatile floating gate memory cells arranged in a plurality of one or more rows and columns, a plurality of one or more of said cells electrically coupled to form a plurality of one or more pages, each of said cells having a first region, a spaced apart second region, a channel region between said first and second regions, a floating gate, and a control gate, said array comprising:

a plurality of page-word lines, each said page-word line connects to said control gate of one or more of said memory cells in one of said pages;

a plurality of page-source lines, each said page-source line connects to said second region of all of said memory cells in one of said pages;

a plurality of bit lines, each said bit line connects to said first region of all of said memory cells in one of said memory-cell-columns;

a plurality of control circuits arranged in rows and columns, each said control circuit selectively couples signals to said page-word lines and said page-source lines of said pages;

a plurality of control-circuit-row lines, each said control-circuit-row line connects to all of said control circuits in a control-circuit-row, each said control-circuit-row line enables said selective coupling in all of said control circuits in said control-circuit-row;

a plurality of word lines, one or more of said word lines connect to all of said control circuits in each of said control-circuit-columns, said plurality of word lines are selectively coupled to said page-word lines by said control circuits;

a plurality of source lines, one or more of said source lines connect to all of said control circuits in each of said control-circuit-columns, said plurality of source lines are selectively coupled to said plurality of page-source lines by said control circuits.

2. The array of non-volatile floating gate memory cells of claim 1 wherein each of said plurality of control circuits comprise:

a transistor circuit adapted to couple said source lines and said word lines to said page-source lines and said page-word lines dependant on the voltage level of said control-circuit-row line.

3. The array of non-volatile floating gate memory cells of claim 1 wherein the physical layout of said array comprises:

a first column and a spaced apart second column, said first and second columns having said electrical coupling for said memory cells to form said plurality of pages and said control circuitry for said plurality of pages;

a third column of non-volatile floating gate memory cells between said first and second columns.

4. The array of non-volatile floating gate memory cells of claim 3 wherein the physical layout of said array further comprises aligning said control circuitry and said electrical coupling of said first and second columns with the corresponding one or more of said plurality of pages of said third column of memory cells.

5. The array of non-volatile floating gate memory cells of claim 1 wherein each of said memory cells are of the type having a first region, a spaced apart second region, a channel region between said first and second regions, a floating gate disposed over at least a portion of said channel region and insulated from said channel region, a control gate disposed over at least a portion of said floating gate and over any portion of said channel region that said floating gate is not disposed over, said control gate insulated from said channel region and said floating gate, said floating gate and/or said control gate disposed over and insulated from a portion of said first region and a portion of said second region.

6. The array of non-volatile floating gate memory cells of claim 5 wherein each of said memory cells are of the type where said floating gate is disposed over and insulated from a portion of said channel region and a portion of said second region and said control gate is disposed over and insulated from said floating gate and portion of said channel region that said floating gate is not disposed over, said control gate is disposed over and insulated from a portion of said first region.

7. An embedded microprocessor for smart card applications comprising:

an array of ROM, said ROM adapted to store BIOS code;

a first array of FLASH EEPROM cells adapted to store program code, said first array of FLASH EEPROM cells implemented as OTPROM; and

,

a second array of FLASH EEPROM cells adapted to store data, said second array of FLASH EEPROM cells having reduced-page-size erase and program operations.

8. The embedded microprocessor of claim 7 wherein said second array of FLASH EEPROM cells comprises:

a plurality of pages, each of said pages having one or more FLASH EEPROM cells electrically coupled;

a plurality of control circuits corresponding to said pages, said control circuits selectively couple signals to said pages;

a plurality of control signals corresponding to said plurality of said control circuits, said control signals enable said selective coupling by said control circuits to said pages; and

,

wherein both said erase and program operations of said FLASH EEPROM can be performed on at least a portion of said FLASH EEPROM cells of said pages having said signals selectively coupled by said corresponding control circuits.

9. The embedded microprocessor of claim 7 wherein said second array of FLASH EEPROM cells comprises:

a plurality of one or more of said cells electrically coupled to form a plurality of pages, each of said cells having a first region, a spaced apart second region, a channel region between said first and second regions, a floating gate, and a control gate;

a plurality of page-word lines, each said page-word line connects to said control gate of one or more of said memory cells in one of said pages;

a plurality of page-source lines, each said page-source line connects to said second region of all of said memory cells in one of said pages;

a plurality of bit lines, each said bit line connects to said first region of all of said memory cells in one of said memory-cell-columns;

a plurality of control circuits arranged in rows and columns, each said control circuit selectively couples signals to both said page-word lines and said page-source lines of one or more of said pages;

a plurality of control-circuit-row lines, each said control-circuit-row line connects to all of said control circuits in a control-circuit-row, each said control-circuit-row line enables said selective coupling in all of said control circuits in said control-circuit-row;

a plurality of word lines, one or more of said word lines connect to all of said control circuits in each of said control-circuit-columns, said plurality of word lines are selectively coupled to said page-word lines by said control circuits;

a plurality of source lines, one or more of said source lines connect to all of said control circuits in each of said control-circuit-columns, said plurality of source lines are selectively coupled to said plurality of page-source lines by said control circuits.