Packet switch control with layered software

• US 6,400,925 B1
• Filed: 02/25/1999
• Issued: 06/04/2002
• Est. Priority Date: 02/25/1999
• Status: Expired due to Term

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: TRW Limited (Zeppelin - Stiftung der Stadt Friedrichshafen)
• Inventors: Arenberg, Edward A., Tirabassi, Maria A.
• Primary Examiner(s): Le, Thanh Cong
• Assistant Examiner(s): Nguyen, Thuan T.
• Application Number:
  US09/258,167
• Time in Patent Office: 1,195 Days
• Field of Search: 455/12.1, 455/13.1, 455/427, 455/428, 455/429, 455/430
• US Class Current: 455/12.1
• CPC Class Codes: H04B 7/18515 Transmission equipment in satellites or space-based relays
• CPC Class Codes: H04B 7/18589 Arrangements for controlling an end to end session, i.e. for initialising, synchronising or terminating an end to end link
• CPC Class Codes: H04L 2012/5608 Satellite
• CPC Class Codes: H04L 2012/5627 Fault tolerance and recovery
• CPC Class Codes: H04L 49/203 ATM switching fabrics with multicast or broadcast capabilities
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/255 Control mechanisms for ATM switching fabrics
• CPC Class Codes: H04L 49/3081 ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 49/552 by ensuring the integrity of packets received through redundant connections
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

A communications satellite (201) has an on-board high speed packet switch for switching transmitted data packets. The packet switch (502) is part of a processor subsystem (501) which also includes a number of demodulators (503₁ to 503_n) demodulating signals received from an uplink downconverter. All of the processors in the processor subsystem (501) are organized into a loosely coupled, distributed, architecture of general purpose computer modules (601) and digital signal processor modules (602) having both primary and redundant processors and being connected to each other by dual redundant PCI buses. Software and firmware is layered and distributed redundantly over the processor modules (601, 602).

Claims

1. A communications satellite comprising:

an up-link sub-system having a downconverter receiving a wideband signal transmission containing information organized into data packets and a demodulator and decoder demodulating the wideband signal transmission and decoding the information to obtain the data packets;

a processor subsystem having a high speed switch receiving a plurality of data packets from the up-link subsystem, switching the data packets, and providing the data packets at output ports thereof, the processor subsystem comprising a plurality of coupled independent processors;

software and firmware layered and distributed over the plurality of independent processors; and

a down-link subsystem receiving the data packets output by the packet switch of the processor subsystem and modulating the data packets in a down link transmission,

wherein the plurality of coupled independent processors operate under control of said layered software and firmware.

2. The communications satellite recited in claim 1, wherein said plurality of independent processors comprises both general processors and digital signal processors.

3. The communications satellite recited in claim 2, wherein a resource controller provides switch management for said high speed packet switch and controls said plurality of independent processors.

4. The communications satellite recited in claim 1, wherein the bottom layer of said layered software and firmware comprises firmware optimized for specific hardware control or data movement.

5. The communications satellite recited in claim 4, wherein the layer immediately above said firmware optimized for specific hardware control or data movement comprises a real-time operating system for general purpose processing.

6. The communications satellite recited in claim 5, wherein the layer immediately above said real-time operating system for general purpose processing comprises software executives optimized for said digital signal processors and embedded I/O control functions.

7. The communications satellite recited in claim 6, wherein the layer immediately above said software executives optimized for said digital signal processors and embedded I/O control functions comprises application software distributed and optimized to each digital signal processor and general processor.

8. The communications satellite recited in claim 7, wherein said application software comprises a fault management program which detects faults in said plurality of independent processors.

9. A high speed packet switch comprising:

a plurality of inbound modules;

a switch fabric receiving data packets from said plurality of inbound modules at a plurality of input ports thereof and switching said data packets to be controllably output from output ports thereof;

a plurality of outbound modules, said plurality of outbound modules receiving said data packets from said output ports of said switch fabric;

software and firmware layered and distributed over a plurality of coupled, independent processors implementing said inbound modules, switch fabric and outbound modules; and

a resource controller controlling each of said inbound modules, switch fabric and outbound modules,

wherein said inbound modules, switch fabric and outbound modules, and resources controller operate under control of said layered software and firmware.

10. The high speed packet data switch recited in claim 9, wherein said plurality of independent processors comprises both general processors and digital signal processors.

11. The communications satellite recited in claim 10, wherein said resource controller provides switch management for said high speed packet switch and controls said plurality of independent processors.

12. The communications satellite recited in claim 9, wherein the bottom layer of said layered software and firmware comprises firmware optimized for specific hardware control or data movement.

13. The communications satellite recited in claim 12, wherein the layer immediately above said firmware optimized for specific hardware control or data movement comprises a real-time operating system for general purpose processing.

14. The communications satellite recited in claim 13, wherein the layer immediately above said real-time operating system for general purpose processing comprises software executives optimized for said digital signal processors and embedded I/O control functions.

15. The communications satellite recited in claim 14, wherein the layer immediately above said software executives optimized for said digital signal processors and embedded I/O control functions comprises application software distributed and optimized to each digital signal processor and general processor.

16. The communications satellite recited in claim 15, wherein said application software comprises a fault management program which detects faults in said plurality of loosely coupled independent processors.