Multitasking during BIOS boot-up
DCFirst Claim
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1. A method to perform multitasking in a basic input and output system (BIOS) by a processor, the method comprising:
- enabling interrupt signals at predetermined interrupt times;
performing a first task in response to the interrupt signals at the interrupt times; and
performing a second task between the successive interrupt times.
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Accused Products
Abstract
The present invention is a method and apparatus to perform multitasking in a basic input and output system (BIOS). Interrupt signals are enabled at predetermined interrupt times. A first task is performed in response to the interrupt signals at the interrupt times. A second task is performed between the successive interrupt times.
128 Citations
40 Claims
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1. A method to perform multitasking in a basic input and output system (BIOS) by a processor, the method comprising:
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enabling interrupt signals at predetermined interrupt times;
performing a first task in response to the interrupt signals at the interrupt times; and
performing a second task between the successive interrupt times. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
disabling the first task after the second task is completely performed.
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3. The method of claim 2 wherein the first task is performed repetitively at each interrupt time.
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4. The method of claim 3 wherein the first task includes a graphic animation.
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5. The method of claim 4 wherein the predetermined interrupt times are sufficiently long to allow the graphic animation to be performed without noticeable flickering.
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6. The method of claim 2 wherein the second task includes device testing and initialization.
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7. The method of claim 2 wherein the first task is performed by code residing on a device accessible to the processor.
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8. The method of claim 2 wherein the second task is part of the BIOS.
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9. The method of claim 1 wherein enabling the interrupt signals comprises:
configuring an interrupt controller to generate the interrupt signals at the predetermined interrupt times.
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10. The method of claim 1 wherein enabling the interrupt signals comprises:
scheduling an interval timer to generate the interrupt signals at the predetermined interrupt times.
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11. A computer program product comprising:
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a computer usable medium having computer program code embodied therein to perform multitasking in a basic input and output system (BIOS) by a processor, the computer program product having;
computer readable program code for enabling interrupt signals at predetermined interrupt times;
computer readable program code for performing a first task in response to the interrupt signals at the interrupt times; and
computer readable program code for performing a second task between the successive interrupt times. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
computer readable program code for disabling the first task after the second task is completely performed.
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13. The computer program product of claim 12 wherein the first task is performed repetitively at each interrupt time.
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14. The computer program product of claim 13 wherein the first task includes a graphic animation.
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15. The computer program product of claim 14 wherein the predetermined interrupt times are sufficiently long to allow the graphic animation to be performed without noticeable flickering.
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16. The computer program product of claim 12 wherein the second task includes device testing and initialization.
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17. The computer program product of claim 12 wherein the first task is performed by code residing on a device accessible to the processor.
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18. The computer program product of claim 12 wherein the second task is part of the BIOS.
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19. The computer program product of claim 11 wherein the computer readable program code for enabling the interrupt signals comprises:
computer readable program code for configuring an interrupt controller to generate the interrupt signals at the predetermined interrupt times.
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20. The computer program product of claim 11 wherein the computer readable program code for enabling the interrupt signals comprises:
computer readable program code for scheduling an interval timer to generate the interrupt signals at the predetermined interrupt times.
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21. A computer data signal embodied in a carrier wave comprising:
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a multitasking code segment to perform multitasking in a basic input and output system (BIOS) by a processor, the multitasking code segment having;
an interrupt enable code segment for enabling interrupt signals at predetermined interrupt times;
a first task code segment for performing a first task in response to the interrupt signals at the interrupt times; and
a second task code segment for performing a second task between the successive interrupt times. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)
a disable code segment for disabling the first task after the second task is completely performed.
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23. The computer data signal of claim 22 wherein the first task is performed repetitively at each interrupt time.
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24. The computer data signal of claim 23 wherein the first task includes a graphic animation.
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25. The computer data signal of claim 24 wherein the predetermined interrupt times are sufficiently long to allow the graphic animation to be performed without noticeable flickering.
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26. The computer data signal of claim 22 wherein the second task includes device testing and initialization.
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27. The computer data signal of claim 22 wherein the first task is performed by code residing on a device accessible to the processor.
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28. The computer data signal of claim 22 wherein the second task is part of the BIOS.
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29. The computer data signal of claim 21 wherein the interrupt enable code segment comprises:
a configuration code segment for configuring an interrupt controller to generate the interrupt signals at the predetermined interrupt times.
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30. The computer data signal of claim 21 wherein the interrupt enable code segment comprises:
a scheduler code segment for scheduling an interval timer to generate the interrupt signals at the predetermined interrupt times.
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31. A system comprising;
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a processor; and
a memory coupled to the processor, the memory containing a program code, the program code when executed by the processor causing the processor to;
enable interrupt signals at predetermined interrupt times, perform a first task in response to the interrupt signals at the interrupt times, and perform a second task between the successive interrupt times. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39, 40)
disable the first task after the second task is completely performed.
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33. The system of claim 32 wherein the first task is performed repetitively at each interrupt time.
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34. The system of claim 33 wherein the first task includes a graphic animation.
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35. The system of claim 34 wherein the predetermined interrupt times are sufficiently long to allow the graphic animation to be performed without noticeable flickering.
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36. The system of claim 32 wherein the second task includes device testing and initialization.
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37. The system of claim 32 wherein the first task is performed by code residing on a device accessible to the processor.
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38. The system of claim 32 wherein the second task is part of the BIOS.
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39. The system of claim 31 wherein the program code causing the processor to enable the interrupt signals by causing the processor to:
configure an interrupt controller to generate the interrupt signals at the predetermined interrupt times.
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40. The system of claim 31 wherein the program code causing the processor to enable the interrupt signals by causing the processor to:
schedule an interval timer to generate the interrupt signals at the predetermined interrupt times.
Specification