Electronic system with self-test function and simulation circuit for electronic system

• US 6,401,226 B1
• Filed: 07/08/1999
• Issued: 06/04/2002
• Est. Priority Date: 03/16/1999
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Maeno, Hideshi
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Chase, Shelly A
• Application Number:
  US09/348,839
• Time in Patent Office: 1,062 Days
• Field of Search: 714/726-728, 714/732-733, 714/738
• US Class Current: 714/728
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

An electronic system with a self-test function has a pseudo-random test pattern generator that serially generates data constituting a pseudo-random test pattern, and stores a 1-bit shifted pseudo-random test pattern obtained by shifting the pseudo-random test pattern by one bit. When a scan-path circuit supplies the pseudo-random test pattern to a tested circuit which carries out an operation based on the pseudo-random test pattern, and then loads an operation result of the tested circuit, the 1-bit shifted pseudo-random test pattern is supplied to the tested circuit as the next pseudo-random test pattern. This makes it possible to solve a problem of a conventional electronic system in that it takes a long time to evaluate the operation results of the tested circuit because it takes at least (1+n)×m clock cycles, where m is the number of pseudo-random test patterns supplied to the tested circuit and n is the number of stages of the scan-path circuit.

Claims

1. An electronic system with a self-test function comprising:

a pseudo-random test pattern generator for serially outputting data constituting a pseudo-random test pattern;

a scan-path circuit for capturing the pseudo-random test pattern by receiving the data serially output from the pseudo-random test pattern generator, for supplying the pseudo-random test pattern in parallel to a tested circuit, for receiving in parallel an operation result of the tested circuit, and for serially outputting data constituting the operation result;

a data compression circuit for compressing the operation result by receiving the data serially output from said scan-path circuit; and

a memory for storing, when said pseudo-random test pattern generator begins to serially output the data constituting the pseudo-random test pattern, a seed of a 1-bit shifted pseudo-random test pattern that is obtained by shifting the pseudo-random test pattern that is obtained by shifting the pseudo-random test pattern by one bit,

wherein said pseudo-random test pattern generator serially supplies said scan-path circuit with data constituting the 1-bit shifted pseudo-random test pattern when said scan-path circuit loads the operation result of the tested circuit in parallel.

2. The electronic system with a self-test function according to claim 1, further comprising a comparator for comparing the operation result compressed by said data compression circuit with expected values.

3. The electronic system with a self-test function according to claim 1, wherein said data compression circuit comprises an exclusive OR circuit and a serial shift register, and wherein said exclusive OR circuit receives data output from a final stage of said serial shift register and data serially output from said scan-path circuit, and supplies an initial stage of said serial shift register with data output from said exclusive OR circuit.

4. The electronic system with a self-test function according to claim 3, wherein said scan-path circuit comprises a greater number of flip-flops than a number of output terminals of said tested circuit, from which the operation result is output in parallel, and wherein each of said flip-flops not connected to the output terminals of the tested circuit loads a fixed value when said scan-path circuit loads the operation result of the tested circuit in parallel.

5. The electronic system with a self-test function according to claim 3, further comprising, between said scan-path circuit and said data compression circuit, a gate circuit for placing the serial output of said scan-path circuit at a fixed value when said scan-path circuit comprises a greater number of flip-flops than a number of output terminals of said tested circuit, from which the operation result is output in parallel.