Method and apparatus for performing both negative and positive slack time budgeting and for determining a definite required constraint during integrated circuit design

• US 6,401,231 B1
• Filed: 04/25/1997
• Issued: 06/04/2002
• Est. Priority Date: 04/25/1997
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Belkhale, Krishna, Limqueco, Johnson Chan
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US08/845,785
• Time in Patent Office: 1,866 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 395/500, 395/500.07, 395/500.4, 395/500.11, 716/6, 716/4, 716/10, 716/18
• US Class Current: 716/108
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

Two time budgeting techniques are provided that are suitable for early and late integrated circuit design phases, respectively. During the early design phase, both the positive and negative slack paths are time budgeted, such that a positive slack path cannot become a negative slack path after budget generation. If all the budget constraints are met by resynthesis for all circuit modules, then the technique guarantees that the final design, when assembled, meets all time constraints. During the late design phase, convergence is guaranteed. Further, synthesis runs for sub-modules focus initially on the worst critical path.

Claims

1. A storage medium containing a computer program for operating a computer to implement a synthesis system that determines time budgeting during integrated circuit design, said computer program comprising a method comprising the steps of:

using positive and negative slack budgeting to determine a budgeted arrival time for all sub-modules of a complete netlist during an initial design phase of said integrated circuit, wherein said budgeted arrival time is based upon a changeable delay of a path, which changeable delay comprises a sum of delays of edges of paths within said integrated circuit whose delays are not fixed, determination of said budgeted arrival time comprising the steps of;

determining a budget arrival time constraint for each input port of each sub-module of said integrated circuit; and

determining a budget required time constraint for each output port of each sub-module of said integrated circuit;

wherein a positive slack path never turns into a negative slack path

after budget generation;

determining a definite required time constraint during a final design phase of said integrated circuit, wherein said definite required time constraint sets an upper bound for an arrival time at each output port of each sub-module within said integrated circuit which requires that arrival at said output port be equal to or greater than than a value produced during a global timing analysis run, said definite required time constraint step further comprising the step of;

determining a relaxed arrival time during said final design phase of said integrated circuit, wherein said relaxed arrival time shifts arrival constraints at each input port of each sub-module forward, where the amount of such shift forward depends upon slack of said input port; and

wherein said shifted arrival time plus a net delay comprises said definite required time constraint for said output port; and

using said budgeted arrival time and said definite required time constraint during a synthesis step in the design of said integrated circuit.

2. The method of claim 1, further comprising the step of:

determining negative slack based upon a changeable delay of a path that causes both a worst determined arrival time at a sub-module port and a worst determined required time at said sub-module port.

3. The method of claim 1, further compromising the step of:

determining positive slack based upon a maximum changeable delay of any path to a sub-module port and any path from said sub-module port.

4. The method of claim 1, further comprising the step of:

fixing wire delays for delay arcs that cross said sub-modules.

5. A synthesis system that determines time budgeting during integrated circuit design, comprising:

a module for using positive and negative slack budgeting to determine a budgeted arrival time for all sub-modules of a complete netlist during an initial design phase of said integrated circuit, wherein said budgeted arrival time is based upon a changeable delay of a path, which changeable delay comprises a sum of delays of edges of paths within said integrated circuit whose delays are not fixed, determination of said budgeted arrival time comprising the steps of;

determining a budget arrival time constraint for each input port of each sub-module of said integrated circuit; and

determining a budget required time constraint for each output port of each sub-module of said integrated circuit;

wherein a positive slack path never turns into a negative slack path after budget generation;

a module for determining a definite required time constraint during a final design phase of said integrated circuit, wherein said definite required constraint sets an upper bound for an arrival time at each output port of each sub-module within said integrated circuit which requires that arrival at said output port be equal to or greater than a value produced during a global timing analysis run, said definite required constraint comprising the step of;

determining a relaxed arrival time during said final design phase of said integrated circuit, wherein said relaxed arrival time shifts arrival time constraints at each input port of each sub-module forward, where the amount of such shift forward depends upon slack of said input port; and

wherein said shifted arrival time plus a net delay comprises said definite required time constraint for said output port; and

a module for using said budgeted arrival time and said definite required time constraint during a synthesis step in the design of said integrated circuit.

6. The apparatus of claim 5, further comprising the step of:

determining negative slack based upon a changeable delay of a path that causes both a worst arrival time at a sub-module port and a worst required time at said sub-module port.

7. The apparatus of claim 5, further comprising the step of:

determining positive slack based upon a maximum changeable delay of any path to a sub-module port and any path from said sub-module port.

8. The apparatus of claim 5, further comprising the step of:

fixing wire delays for delay arcs that cross said sub-modules.

9. In a computer including a processor and memory, a computer program resident in said computer'"'"'s memory for operating said computer to implement a synthesis system that determines time budgeting during integrated circuit design, said computer program comprising a method comprising the steps of:

using positive and negative slack budgeting to determine a budgeted arrival time for all sub-modules of a complete netlist during an initial design phase of said integrated circuit;

determining a definite required time constraint during a synthesis step in a final design phase of said integrated circuit; and

using said budgeted arrival time and said definite required time constraint during said synthesis step in the design of said integrated circuit.