Process for fabricating organic semiconductor device involving selective patterning

• US 6,403,397 B1
• Filed: 06/28/2000
• Issued: 06/11/2002
• Est. Priority Date: 06/28/2000
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Guardian Corp. (Broadcom, Inc.)
• Inventors: Katz, Howard Edan
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Dang, Phuc T.
• Application Number:
  US09/605,507
• Time in Patent Office: 713 Days
• Field of Search: 438/29, 438/35, 438/55, 438/82, 438/99, 438/151, 438/455, 438/780, 438/149, 438/164, 438/237, 438/328, 438/466, 438/584
• US Class Current: 438/99
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 71/13 using printing techniques, e.g. ink-jet printing or screen printing
• CPC Class Codes: H10K 71/20 Changing the shape of the active layer in the devices, e.g. patterning

Abstract

An improved process for forming devices utilizing patterned organic semiconductor films is provided. The process involves treating a surface to selectively provide regions of greater affinity and lesser affinity for an organic semiconductor or an organic semiconductor solution. When the organic semiconductor, or solution comprising the semiconductor, is deposited on the treated surface, either the organic semiconductor or the organic semiconductor solution dewets from the lesser affinity regions or the resultant film adheres only weakly to the lesser affinity regions such that selective removal is readily performed. And even where such removal is not performed, the portions of the organic semiconductor film overlying the greater affinity regions exhibit higher mobility and better film continuity relative to the other portions of the film.

Claims

1. A process for fabricating a device, comprising the steps of:

providing a surface;

treating the surface to selectively provide at least one region of greater affinity for an organic semiconductor or an organic semiconductor solution and at least one region of lesser affinity for the organic semiconductor or the organic semiconductor solution; and

forming on the treated surface an organic semiconductor film from the organic semiconductor or the organic semiconductor solution.

2. The process of claim 1, further comprising the step of at least partially removing the portion of the organic semiconductor film formed on the at least one region of lesser affinity.

3. The process of claim 2, wherein substantially all the organic semiconductor film is removed from the at least one region of lesser affinity.

4. The process of claim 1, wherein the step of forming comprises depositing the organic semiconductor solution on the treated surface, and evaporating the solvent.

5. The process of claim 4, wherein substantially no organic semiconductor solution wets the at least one region of lesser affinity film, such that the at least one region of lesser affinity comprises substantially no organic semiconductor film after evaporation of the solvent.

6. The process of claim 1, wherein the provided surface comprises a dielectric material.

7. The process of claim 6, wherein the provided surface further comprises metal contacts.

8. The process of claim 7, wherein the device comprises a field effect transistor that further comprises a gate.

9. The process of claim 1, wherein the regions of greater affinity or lesser affinity are created by providing the surface with selected moieties or by formation of a continuous or discontinuous polymer film on the surface.

10. The process of claim 9, wherein the treating step comprises forming the continuous or discontinuous polymer film onto a dielectric film, and wherein the dielectric constant of the polymer film is less than or comparable to that of the dielectric film.

11. The process of claim 10, wherein the device is a field effect transistor further comprising source and drain contacts and a gate, wherein the source and drain contacts at least partially overlap both the gate electrode and regions where the polymer film is formed on the dielectric film, and wherein the device exhibits a lower circuit capacitance associated with the regions where the source and drain contacts at least partially overlap both the gate electrode and the regions where the polymer film is formed on the dielectric film.

12. The process of claim 1, wherein the at least one region of greater affinity is provided by selectively providing the surface with moieties that interact favorably with the organic semiconductor material or with the solvent of the organic semiconductor solution relative to the at least one region of lower affinity.

13. The process of claim 1, wherein the at least one region of lesser affinity is provided by selectively providing the surface with moieties that are less compatible with moieties on the organic semiconductor material or with the solvent of the organic semiconductor solution, relative to the at least one region of greater affinity.

14. The process of claim 1, wherein the organic semiconductor film is formed from the organic semiconductor solution, and wherein the solution comprises a solvent that comprises at least one non-aqueous solvent.

15. The process of claim 14, wherein the solvent consists of one or more non-aqueous solvents.

16. The process of claim 15, wherein the non-aqueous solvents are not miscible with water at room temperature.