Wiring substance and semiconductor

• US 6,403,895 B1
• Filed: 02/04/2000
• Issued: 06/11/2002
• Est. Priority Date: 02/10/1999
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Sota, Yoshiki
• Primary Examiner(s): Cureo, Kamand
• Assistant Examiner(s): VU, QUYNH-NHU HOANG
• Application Number:
  US09/497,680
• Time in Patent Office: 858 Days
• Field of Search: 174/260, 174/261, 174/524, 174/262, 174/265, 361/760, 361/761, 361/767, 361/768, 361/777, 361/783, 361/771, 257/784, 257/780
• US Class Current: 174/260
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48599 Principal constituent of the connecting portion of the wire connector being Gold (Au)
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/49433 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19107 : off-chip wires

Abstract

A semiconductor device includes a wiring substrate which includes a wiring pattern provided per each wiring with a land covering an external terminal mounting perforation for mounting an external terminal, said land being provided on a side of the wiring pattern on which side a semiconductor chip is mounted, wherein a plurality of second pads for electrically connecting the wiring and the semiconductor chip by wire bonding are provided per each wiring, and at least one of the second pads is provided between lands.

Claims

1. A wiring substrate comprising:

a wiring pattern formed on a substrate, the wiring pattern provided with at least one wiring and a plurality of separate and distinct conductive lands, each land covering a perforation defined in the substrate, each perforation for mounting an external terminal, each said lands being provided on a side of the substrate on which a semiconductor chip is mounted,

wherein the wiring includes a first one of the lands and a plurality of electrode terminals provided for a wire, the electrode terminals of said wiring being spaced from one another and being electrically connected to one another, and

wherein at least one of the plurality of electrode terminals of the wiring is provided in a space between the first land and a second one of the lands, said first and second lands being provided side by side in a direction extending from a mounting area of the semiconductor chip toward an edge of the substrate.

2. The wiring substrate as set forth in claim 1, wherein at least one of the plurality of electrode terminals is provided outside of a land forming region of the wiring pattern with which the at least one electrode terminal is associated.

3. The wiring substrate as set forth in claim 2, wherein at least one of the plurality of electrode terminals is provided between the land forming region and an edge portion of the substrate.

4. The wiring substrate as set forth in claim 2, wherein at least one of the plurality of electrode terminals is provided between the land forming region and a semiconductor chip mounting region.

5. The wiring substrate as set forth in claim 1, wherein the wiring pattern is made of an electrically conductive material of a single layer.

6. A wiring substrate comprising:

a wiring pattern on a substrate, the wiring pattern provided with a wiring and a plurality of conductive lands covering corresponding perforations, each perforation for mounting an external terminal to the substrate,

wherein the wiring includes a first one of the lands and a plurality of electrode terminals provided for a wire, the electrode terminals of said wiring being spaced from one another and being electrically connected to one another, and

wherein at least one of the plurality of electrode terminals of said wiring is provided in a space between the first land and a second one of the lands outside of a semiconductor chip mounting, region of the substrate.

7. A wiring substrate comprising:

a wiring pattern formed on a substrate, the wiring pattern being provided with a plurality of lands, each land covering a perforation in the substrate that is for mounting an external terminal, each land being provided on a side of the substrate on which a semiconductor chip is mounted,

a wiring of the pattern including a first one of the lands and an electrode terminal provided for a wire,

wherein the electrode terminal of said wiring is provided in a space between the first land and a second one of the lands, wherein the first and second lands are provided side by side in a direction extending from a mounting area of the semiconductor chip to an edge of the substrate, and

relay wiring for electrically connecting the electrode terminal and the semiconductor chip by wire bonding is provided on the substrate between the wiring pattern and a semiconductor mounting region of the substrate.

8. The wiring substrate as set forth in claim 7, wherein said relay wiring includes:

a first electrode pad which is provided for wire bonding and in a vicinity of the wiring pattern, and

a second electrode pad which is provided for wire bonding and in a vicinity of the semiconductor chip mounting region, and which is electrically connected to the first electrode pad.

9. The wiring substrate as set forth in claim 7, wherein said wiring pattern and said relay wiring are each made of an electrically conductive material of a single layer.

10. A semiconductor device comprising:

a wiring substrate which includes a wiring pattern provided with a plurality of separate and distinct lands, each land covering a perforation in the substrate for mounting an external terminal, each land being provided on a side of the substrate on which a semiconductor chip is mounted,

a wiring of the pattern including a first one of the lands and a plurality of electrode terminals provided for a wire, the electrode terminals of said wiring being spaced from one another and being electrically connected to one another, and

wherein at least one of the electrode terminals of the wiring is provided in a space between the first land and a second one of the lands, said first and second lands being provided side by side in a direction extending from a mounting area of the semiconductor chip toward an edge of the substrate.

11. A semiconductor device comprising:

a wiring substrate which includes a wiring pattern with a plurality of lands, each land covering a perforation in the substrate for mounting an external terminal,

a wiring of the wiring pattern including at least a first one of the lands and an electrode terminal provided for a wire,

wherein the electrode terminal of the wiring is provided in a space between the first land and a second one of the lands, and relay wiring for electrically connecting the electrode terminal and the semiconductor chip by wire bonding is provided on the substrate.