Thin film capacitors on silicon germanium substrate

• US 6,404,003 B1
• Filed: 07/28/1999
• Issued: 06/11/2002
• Est. Priority Date: 07/28/1999
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation), Symetrix Corporation
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation), Symetrix Corporation
• Inventors: Paz de Araujo, Carlos A., Arita, Koji, McMillan, Larry D., Azuma, Masamichi
• Primary Examiner(s): Tran, Minh Loan
• Application Number:
  US09/362,480
• Time in Patent Office: 1,049 Days
• Field of Search: 257/301-310, 257/616, 257/311, 257/532, 257/535, 361/303, 361/305
• US Class Current: 257/306
• CPC Class Codes: C23C 18/1216 Metal oxides C23C18/1212 takes precedence
• CPC Class Codes: C23C 18/1245 Inorganic substrates other than metallic
• CPC Class Codes: C23C 18/1279 performed under reactive atmosphere, e.g. oxidising or reducing atmospheres
• CPC Class Codes: C23C 18/1283 Control of temperature, e.g. gradual temperature increase, modulation of temperature
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 28/75 comprising two or more layers, e.g. comprising a barrier layer and a metal layer

Abstract

An integrated circuit capacitor containing a thin film delectric metal oxide is formed above a silicon germanium substrate. A silicon nitride diffusion barrier layer is deposited on a silicon germanium substrate to prevent evaporation of the substrate in subsequent heating steps. A silicon dioxide stress reduction layer is deposited on the diffusion barrier layer. A bottom electrode is formed on the stress reduction layer, then a liquid precursor is spun on the bottom electrode, dried at about 400° C., and annealed at between 600° C. and 850° C. to form a BST capacitor dielectric. A top electrode is deposited on the dielectric and annealed. The integrated circuit may also include a BiCMOS device, a HBT device or a MOSFET.

Claims

1. A high capacitance thin film capacitor device comprising:

a silicon germanium substrate;

a capacitor, said capacitor comprising a bottom electrode, a top electrode, and a thin film of dielectric metal oxide between said electrodes;

a diffusion barrier layer located directly on said silicon germanium substrate between said substrate and said capacitor; and

a stress reduction layer located between said silicon germanium substrate and said bottom electrode.

2. A high capacitance thin film capacitor device as in claim 1 wherein said metal oxide comprises barium strontium titanate.

3. A high capacitance thin film capacitor device as in claim 2 wherein said barium strontium titanate is represented by a chemical formula (Ba_1-xSr_x)TiO₃, where 0>

x>

1.

4. A high capacitance thin film capacitor device as in claim 3 wherein said barium strontium titanate is represented by a chemical formula (Ba_0.7Sr_0.3)TiO₃.

5. A high capacitance thin film capacitor device as in claim 1 wherein said metal oxide comprises a layered superlattice material.

6. A high capacitance thin film capacitor device as in claim 5 wherein said layered superlattice material is ferroelectric.

7. A high capacitance thin film capacitor device as in claim 5 wherein said layered superlattice material is nonferroelectric.

8. A high capacitance thin film capacitor device as in claim 1 wherein said metal oxide comprises a perovskite compound.

9. A high capacitance thin film capacitor device as in claim 8 wherein said perovskite compound is ferroelectric.

10. A high capacitance thin film capacitor device as in claim 8 wherein said perovskite compound is nonferroelectric.

11. A high capacitance thin film capacitor device as in claim 1 wherein said diffusion barrier layer comprises Si₃N₄.

12. A high capacitance thin film capacitor device as in claim 1 wherein said stress reduction layer is located between said diffusion barrier layer and said bottom electrode.

13. A high capacitance thin film capacitor device as in claim 12 wherein said stress reduction layer is located directly on said diffusion barrier layer.

14. A high capacitance thin film capacitor device as in claim 12 wherein said stress reduction layer comprises silicon dioxide.

15. A high capacitance thin film capacitor device as in claim 12 wherein said stress reduction layer comprises a glasseous oxide.

16. A high capacitance thin film capacitor device as in claim 1 wherein said bottom electrode comprises an adhesion layer and an electrode layer.

17. A high capacitance thin film capacitor device as in claim 16 wherein said adhesion layer comprises a material selected from the group consisting of titanium, tantalum, nickel, tantalum silicide, nickel silicide, and palladium.

18. A high capacitance thin film capacitor device as in claim 16 wherein said electrode layer comprises platinum.

19. A high capacitance thin film capacitor device as in claim 1 wherein said stress reduction layer comprises silicon dioxide.

20. A high capacitance thin film capacitor device as in claim 1 wherein said stress reduction layer comprises a glasseous oxide.

21. A high capacitance thin film capacitor device as in claim 1 wherein said silicon germanium substrate comprises a silicon germanium wafer.

22. A high capacitance thin film capacitor device as in claim 1 wherein said silicon germanium substrate comprises a silicon semiconductor wafer.

23. A high capacitance thin film capacitor device as in claim 1 wherein said silicon germanium substrate comprises a silicon germanium region.

24. A high capacitance thin film capacitor device as in claim 23 wherein said silicon germanium region comprises a crystal lattice having relative amounts of silicon and germanium atoms represented by a stoichiometric formula Si_1-xGe_x, in which 0<

x<

1.

25. A high capacitance thin film capacitor device as in claim 23 wherein said silicon germanium region comprises a silicon germanium layer.

26. A high capacitance thin film capacitor device as in claim 1 wherein said silicon germanium substrate comprises a silicon germanium device portion.