Trench transistor with superior gate dielectric

• US 6,404,007 B1
• Filed: 04/05/1999
• Issued: 06/11/2002
• Est. Priority Date: 04/05/1999
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Mo, Brian Sze-Ki, Chau, Duc
• Primary Examiner(s): Ngô , Ngân V.
• Application Number:
  US09/286,168
• Time in Patent Office: 1,163 Days
• Field of Search: 257/324, 257/325, 257/326, 257/330, 257/332
• US Class Current: 257/324
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench transistor with lower leakage current and higher gate rupture voltage. The gate oxide layer of a trench transistor is grown at a temperature above about 1100° C. to reduce thinning of the oxide layer at the corners of the trench. In a further embodiment, a conformal layer of silicon nitride is deposited over the high-temperature oxide layer, and a second oxide layer is formed between the silicon nitride layer and the gate polysilicon. The first gate oxide layer, silicon nitride layer, and second oxide layer form a composite gate dielectric structure that substantially reduces leakage current in trench field effect transistors.

Claims

1. A trench field effect transistor, comprising:

a substrate of a first conductivity type, the substrate embodying a drain of the transistor;

a body layer of a second conductivity type formed over the substrate, the body layer having an upper surface;

a trench extending through the body layer and into the substrate, the trench defined by upper corners at the upper surface of the body layer, lower corners at the bottom of the trench, and walls formed therebetween;

a dielectric layer lining the walls, lower corners and bottom of the trench, thereby forming a dielectric-lined trench;

a conductive gate material lining the entire bottom and substantially filling the dielectric-lined trench; and

a source region of the first conductivity type flanking the trench,

wherein the dielectric layer comprises a first oxide layer lining the walls, lower corners and bottom of the trench, a silicon nitride layer disposed on the first oxide layer, and a second oxide layer disposed between the silicon nitride layer and the conductive gate material.

2. The trench transistor of claim 1, wherein the first oxide layer has a first thickness of at least about 300 Å

, the silicon nitride layer has a second thickness of about 120 Å

, and the second oxide layer has a third thickness of about 50 Å

.

3. A trench field effect transistor, comprising:

a substrate of a first conductivity type, the substrate embodying the drain of the transistor;

a body layer of a second conductivity type formed over the substrate;

a trench extending through the body layer and into the substrate;

a first oxide layer thermally grown on walls and bottom of the trench;

a silicon nitride layer disposed on the first oxide layer;

a second oxide layer disposed on the silicon nitride layer, thereby forming a second-oxide-lined trench having a bottom surface and sidewalls; and

a conductive gate material lining the entire bottom surface and substantially filling the second-oxide-lined trench.

4. The trench transistor of claim 3, wherein the first oxide layer is grown at a temperature of at least about 1,100°

C.

5. The trench transistor of claim 4, wherein the first oxide has a thickness of about 300 Å

.

6. The trench transistor of claim 5, wherein the silicon nitride layer has a thickness of about 120 Å

.

7. The trench transistor of claim 6, wherein the second oxide layer has a thickness of about 50 Å

.