Semiconductor power integrated circuit

• US 6,404,011 B2
• Filed: 05/23/2001
• Issued: 06/11/2002
• Est. Priority Date: 10/28/1998
• Status: Expired due to Term

• Current Assignee: Uniloc 2017 LLC (FIG LLC (d/b/a Fortress Investment Group LLC))
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Kim, Dae-Yong, Koo, Jin-gun, Kim, Sang-Gi, Kim, Jong-Dae
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US09/865,004
• Publication Number:
  US 20020005562A1
• Time in Patent Office: 384 Days
• Field of Search: 257/341-342, 257/335, 257/339, 257/487-494, 257/500-510
• US Class Current: 257/341
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing steps and obtain a low on-resistance.

Claims

1. A semiconductor power integrated circuit, comprising;

a) a semiconductor structure having a trench with a predetermined depth from a surface of the semiconductor structure, wherein the semiconductor structure includes an active region having a well region for forming a channel and a source, and a drift region for forming a drain region;

b) a trench isolation layer pattern including a first oxide layer and a second oxide layer, wherein the first oxide layer fills inside the trench and has a predetermined thickness from the surface of the semiconductor structure, and wherein the second oxide layer is formed on the first oxide layer and has a predetermined thickness smaller than the second oxide layer;

c) a field oxide layer pattern including a third oxide layer and a fourth oxide layer, wherein the third oxide layer is simultaneously formed with the same layer as the first oxide layer of the field oxide layer pattern and has a predetermined thickness from a surface of the semiconductor structure, and wherein the fourth oxide layer is simultaneously formed with the same layer as the second oxide layer of the field oxide layer of the field oxide layer pattern and has a thickness smaller than the third oxide layer; and

d) a gate oxide layer pattern including a fifth oxide layer and a sixth oxide layer, wherein the fifth oxide layer is simultaneously formed with the same layer as the first oxide layer of the field oxide layer pattern and has a predetermined thickness from a surface of the semiconductor structure, and wherein the sixth oxide layer is simultaneously formed with the same layer as the second oxide layer of the field oxide layer of the field oxide layer pattern and has a thickness smaller than the third oxide layer.

2. The semiconductor power integrated circuit as recited in claim 1, wherein the first and second layers are TEOS-oxide layers.

3. The semiconductor power integrated circuit as recited in claim 2, wherein the predetermined thickness of the first oxide layer is of 8000 Å

to 15000 Å and

the predetermined thickness of the second oxide layer is of 2000 Å

to 5000 Å

.

4. The semiconductor power integrated circuit as recited in claim 3, wherein the semiconductor power device further comprises:

a semiconductor substrate of a first conductivity type;

a buried insulating layer formed on the semiconductor substrate of the first conductivity type; and

an epitaxial layer of a second conductivity type formed on the buried insulating layer.

5. The semiconductor power integrated circuit as recited in claim 4, wherein the predetermined depth of the trench reaches to the epitaxial layer.

6. The semiconductor power integrated circuit as recited in claim 5, wherein the semiconductor power integrated circuit further comprises:

a thermal oxide layer entirely formed on the semiconductor structure of the first conductivity type;

a source region of the second conductivity type formed on the first region of the first conductivity type;

a drain region of the second conductivity type formed on the second region of the second conductivity type; and

a source region of the first conductivity type on the first well region of the first conductivity type.