Deblocking filter for encoder/decoder arrangement and method with divergence reduction

• US 6,404,361 B2
• Filed: 12/11/2000
• Issued: 06/11/2002
• Est. Priority Date: 02/19/1992
• Status: Expired due to Term

• Current Assignee: 8X8, Inc.
• Original Assignee: Netergy Microelectronics, Inc. (8X8, Inc.)
• Inventors: Andrews, Barry D., Ning, Paul, Kwan, Katherine, Chiang, May Shu-Pei, Hu, Ruili, Bryant, Stephane, Voois, Paul A., Martin, Bryan R.
• Primary Examiner(s): YOUNG, BRIAN K
• Application Number:
  US09/734,280
• Publication Number:
  US 20010020906A1
• Time in Patent Office: 547 Days
• Field of Search: 341/94, 341/50, 341/200, 341/65, 348/845.1, 348/420
• US Class Current: 341/94
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: H04N 19/82 involving filtering within a prediction loop
• CPC Class Codes: H04N 19/86 involving reduction of coding artifacts, e.g. of blockiness
• CPC Class Codes: H04N 7/141 between two video terminals, e.g. videophone telephonic communication systems combined with television receiver for reception of entertainment or information matter H04M11/085
• CPC Class Codes: H04N 7/15 Conference systems

Abstract

According to one aspect of the disclosure, the present invention provides methods and arrangements for the removal or reduction of divergence artifacts between a transmitting codec and a receiving codec. One of a number of implementations includes using a deblocking filter in an inverse transformer loop and selectively disabling the filter upon certain conditions.

Claims

1. A method for coding a representation of an image at a first terminal that is adapted to communicate with a second terminal, the method comprising:

operating at least one of the first and second terminals using an inverse transformer loop; and

preventing unacceptable error accumulation within the inverse transformer loop by using the inverse transformer in the loop according to a bit-exact specification between the first and second terminals.

2. The method of claim 1, wherein each of the first and second terminals is adapted to use the inverse transformer loop.

3. The method of claim 1, wherein one of the first and second terminals is adapted to use a coder and the other of the first and second terminals is adapted to use a decoder, and wherein the bit-exact specification is used by the coder and decoder in communication between the first and second terminals.

4. The method of claim 1, wherein each of the first and second terminals is adapted to use a coder and a decoder and with the bit-exact specification used by the coder and decoder in communication in one direction between the first and second terminals.

5. The method of claim 1, further including selecting the bit-exact specification from a plurality of available bit-exact specifications.

6. The method of claim 5, wherein selecting the bit-exact specification is part of a decision negotiated using communication between the first and second terminals.

7. For communicating a representation of an image between a first terminal and a second terminal using a communications channel, an arrangement in at least one of the terminals, comprising:

means for operating said at least one of the terminals using an inverse transformer loop; and

means for preventing unacceptable error accumulation within the inverse transformer loop by using the inverse transformer in the loop according to a bit-exact specification between the first and second terminals.

8. For communicating a representation of an image between a first terminal and a second terminal using a communications channel, an arrangement in at least one of the terminals, comprising:

a programmed video-data processing circuit configured and arranged to operate said at least one of the terminals using an inverse transformer loop, and to prevent unacceptable error accumulation within the inverse transformer loop by using the inverse transformer in the loop according to a bit-exact specification between the first and second terminals.