System and method for achieving slot synchronization in a wideband CDMA system in the presence of large initial frequency errors

• US 6,404,758 B1
• Filed: 04/19/1999
• Issued: 06/11/2002
• Est. Priority Date: 04/19/1999
• Status: Expired due to Term

• Current Assignee: Optis Wireless Technology, LLC (Brevet Capital)
• Original Assignee: Ericsson, Inc. (Telefonaktiebolaget LM Ericsson)
• Inventors: Wang, Yi-Pin Eric
• Primary Examiner(s): Hunter, Daniel
• Assistant Examiner(s): D AGOSTA, STEPHEN M
• Application Number:
  US09/294,644
• Time in Patent Office: 1,149 Days
• Field of Search: 370/335, 370/342, 370/350, 370/441, 370/503, 370/515, 375/143, 375/343, 375/362, 375/363, 375/365, 375/366, 455/39, 455/73, 455/130
• US Class Current: 370/342
• CPC Class Codes: H04B 1/7075 with code phase acquisition
• CPC Class Codes: H04B 1/70754 Setting of search window, i.e. range of code offsets to be searched H04B1/70758 takes precedence
• CPC Class Codes: H04B 1/7093 Matched filter type
• CPC Class Codes: H04B 1/7097 Interference-related aspects
• CPC Class Codes: H04B 1/7115 Constructive combining of multi-path signals, i.e. RAKE receivers

Abstract

A system and method are provided for achieving slot synchronization in a Wideband CDMA system in the presence of large initial frequency errors. A FSC matched filter having a reduced coherence window is provided for reducing degradation of a symbol due to carrier phase rotation resulting from oscillator error, thereby preventing severe loss of signal energy at the peaks of the FSC matched filter output. Additionally, a circular sliding integrator is provided to combine the accumulated disbursed signal energies due to the oscillator error and multipath interference, thereby allowing easier identification of the time index representing the time slot boundary. Further, a sorter is provided for determining a predetermined number of time index candidates representing the time slot boundary, thereby increasing the possibility that the true time index boundary is sent to the second stage of synchronization.

Claims

1. A receiver for improving initial slot synchronization in a Wideband code division multiple access communications system by overcoming oscillator error, the receiver comprising:

a matched filter receiving a signal including a first search code (FSC), the matched filter utilizing a reduced coherence window for decreasing the degradation of a symbol due to a carrier phase rotation resulting from the oscillator error;

an accumulator coupled to the matched filter for accumulating an output of the matched filter over an accumulation window of time slots;

a circular sliding integrator coupled to the accumulator for combining dispersed energy from an output of the accumulator over an integration window; and

a sorter coupled to the circular sliding integrator for determining a specified number of candidate time indices for a time slot boundary using an output of the circular sliding integrator.

2. The receiver of claim 1 wherein the matched filter is a FSC matched filter.

3. The receiver of claim 1 wherein the size of the coherence window is determined using a desired phase rotation, a chip duration, and an actual frequency error due to the oscillator.

4. The receiver of claim 1 wherein the matched filter includes:

a shift register having a number of elements less than a number of chips comprising the symbol, for holding a portion of the received signal;

a multiplying-integrating processing circuit coupled to the shift register for multiplying the portion of the received signal in the shift register with a portion of the FSC, and integrating the products; and

a phase elimination circuit coupled to the multiplying-integrating processing circuit for removing phase information from a result produced by the multiplying-integrating processing circuit.

5. The matched filter of claim 1 wherein the circular sliding integrator is a first integrator, and further comprising:

a shift register having a number of elements equal to a number of chips comprising the symbol for receiving the received signal;

a buffer coupled to the shift register for receiving a portion of the received signal from the shift register;

a multiplying-integrating processing circuit coupled to the buffer for multiplying the portion of the received signal in the buffer with a portion of the FSC, and integrating the products;

a phase elimination circuit coupled to the multiplying-integrating processing circuit for removing phase information from a result produced by the multiplying-integrating processing circuit;

a storage device coupled to the phased elimination circuit for storing a result produced by the phase elimination circuit; and

a second integrator coupled to the storage device for integrating the stored results.

6. The receiver of claim 1 wherein the size of the accumulation window is determined using a signal-to-noise ratio.

7. The receiver of claim 1 wherein size of the integration window is determined using the oscillator error, a chip duration, and size of the accumulation window.

8. A receiver for improving initial slot synchronization in a Wideband code division multiple access communications system by overcoming oscillator error, the receiver comprising:

a matched filter receiving a signal including a first search code (FSC), the matched filter utilizing a reduced coherence window for decreasing degradation of a symbol due to a carrier phase rotation;

an accumulator coupled to the matched filter for accumulating an output of the matched filter over an accumulation window of time slots; and

an integrator coupled to the accumulator for combining dispersed energy from an output of the accumulator over an integration window.

9. The receiver of claim 8 wherein the matched filter is a FSC matched filter.

10. The receiver of claim 8 wherein the size of the coherence window is determined using a desired phase rotation, a chip duration and an actual frequency error due to the oscillator.

11. The receiver of claim 8 wherein the matched filter includes:

a shift register having a number of elements less than a number of chips comprising the symbol, for holding a portion of the received signal;

a multiplying-integrating processing circuit coupled to the shift register for multiplying the portion of the received signal in the shift register with a portion of the first search code, and integrating the products; and

a phase elimination circuit coupled to the multiplying-integrating processing circuit for removing phase information from a result produced by the multiplying-integrating processing circuit.

12. The matched filter of claim 8 wherein the integrator is a first integrator, and further comprising:

a shift register having a number of elements equal to a number of chips comprising the symbol for receiving the received signal;

a buffer coupled to the shift register for receiving a portion of the received signal from the shift register;

a multiplying-integrating processing circuit coupled to the buffer for multiplying the portion of the received signal in the buffer with a portion of the FSC, and integrating the products;

a phase elimination circuit coupled to the multiplying-integrating processing circuit for removing phase information from a result produced by the multiplying-integrating processing circuit;

a storage device coupled to the phased elimination circuit for storing a result produced by the phase elimination circuit; and

a second integrator coupled to the storage device for integrating the stored results.

13. The receiver of claim 8 further comprising a sorter coupled to the integrator for determining a specified number of candidate time indices for a time slot boundary using an output of the integrator.

14. A receiver for improving initial slot synchronization in a Wideband code division multiple access communications system by overcoming oscillator error, the receiver comprising:

a matched filter receiving a signal including a first search code (FSC) for decreasing degradation of a symbol due to a carrier phase rotation;

an accumulator coupled to the matched filter comprising a predetermined number of storage locations for accumulating an output of the matched filter over an accumulation window of time slots; and

an integrator coupled to the accumulator for combining dispersed energy from an output of the accumulator over an integration window.

15. The receiver of claim 14 wherein the size of the integration window is determined using an oscillator error, a chip duration and size of the accumulation window.

16. The receiver of claim 14 wherein the predetermined number of storage locations equals the number of chips comprising the symbol, and the integrator is a sliding integrator wherein the integration window moves across the predetermined number of storage locations.

17. The receiver of claim 16 wherein the sliding integrator is a circular sliding integrator, wherein when the integration window extends beyond a final storage location, the integration window extends to a first storage location, thereby operating in a circular fashion.

18. The receiver of claim 14 further comprising a sorter coupled to the integrator for determining a specified number of candidate time indices for a time slot boundary using an output of the integrator.

19. A method for improving slot synchronization in a Wideband CDMA communications system by overcoming oscillator error, the method comprising:

receiving a signal including a first search code (FSC);

filtering the received signal using a matched filter having a reduced coherence window;

accumulating the filtered signal over an accumulation window of time slots to overcome noise in the filtered signal; and

integrating the accumulated signal over an integration window to combine dispersed energy in the accumulated signal.

20. The method of claim 19 wherein the step of filtering the received signal includes filtering the received signal using a FSC matched filter.

21. The method of claim 19 wherein the step of filtering the received signal includes:

shifting a portion of the received signal in to a shift register;

multiplying the portion of the received signal with a portion of the FSC and integrating the products using a multiplying-integrating processing circuit; and

removing phase information from a result produced by the multiplying-integrating processing circuit using a phase elimination circuit.

22. The method of claim 19 wherein the step of filtering the received signal includes:

shifting the received signal into a shift register;

buffering a portion of the received signal from the shift register;

multiplying the portion of the received signal with a portion of the FSC and integrating the products using a multiplying-integrating processing circuit;

removing phase information from a result produced by the multiplying-integrating processing circuit using a phase elimination circuit;

storing the result of the phase elimination circuit; and

integrating the stored results.

23. The method of claim 19 wherein the step of accumulating the filtered signal further comprises determining a signal-to-noise ratio for the received signal.

24. The method of claim 19 wherein the step of integrating the accumulated signal further comprises moving the integration window across memory locations storing the accumulated signal.

25. The method of claim 24 wherein the step of moving the integration window includes extending the integration window to a first storage location for the accumulated signal when the integration window extends beyond a final storage location for the accumulated signal.

26. The method of claim 19 further comprising the step of determining a specified number of candidate time indices for a time slot boundary using the integrated signal.

27. The method of claim 26 wherein the step of determining the specified number of candidate time indices further includes:

(a) determining a first candidate time index for a largest integrator output value;

(b) zeroing out neighboring time index values of the first candidate time index;

(c) determining an additional candidate time index for a next largest integrator output value and zeroing out the neighboring time index values of the additional candidate time index; and

(d) repeating step (c) until the specified number of candidate time indices is reached.

28. The method of claim 26 further comprising the step of communicating the specified number of determined candidate time indices to a second stage synchronizer.