Memory compiler interface and methodology

• US 6,405,160 B1
• Filed: 08/03/1998
• Issued: 06/11/2002
• Est. Priority Date: 08/03/1998
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Knebelsberger, David William, Nicholes, James W., Hancock, Gary Wayne, Smith, Douglas D., Djaja, Gregory
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): PHAN, THAI Q
• Application Number:
  US09/128,272
• Time in Patent Office: 1,408 Days
• Field of Search: 703/24, 703/21, 703/27, 710/16, 710/38, 365/230, 716/2, 717/11, 717/5, 717/9
• US Class Current: 703/24
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A compilier methodology including a stand alone memory interface which provides a user specified memory device of a required number of words of memory of a required bits per word. The stand alone memory interface is a tool to provide a menu showing multiple ways in which the user'"'"'s request can be physically configured by varying the number of rows of memory, the number of blocks of memory, and the column multiplexing factor of the memory array. From this menu the user selects the memory configuration that best meets the user'"'"'s requirements and is provided with either various models or representations (views) of the selected memory configuration or a GDS format data file. The views can be used to design large scale integrated circuits in which the memory device is embedded while the data file is used to generate photo mask for making the memory device as an integrated circuit.

Claims

1. A memory compiler methodology including a stand alone interface through which an user may specify a certain type of memory device of specific requirements and which will provide the user a menu listing several options of such memory device that meets the user'"'"'s requirement based on a precharacterization of all valid configurations of the type of memory device architecture, comprising the steps of:

1) initially designing a baseline configuration for the memory device architecture from which the user may specify a memory device, including the substeps of;

a) generating the transistor level circuitry for the various circuit blocks comprising the baseline configuration;

b) generating a physical layout and X-Y coordinates to predetermined critical features of the physical layout for each of the various circuit blocks;

c) converting the subsets 1a and 1b into computer code files;

2) compiling all of the computer code files and verifying the functionality thereof across all architectural variables;

3) selecting a small number of subsets of all possible configurations of the memory device;

4) statistically analyzing each of the subsets to derive characteristic mathematical equations which represent key parameters and properties for all valid configurations of the memory device;

5) compiling all of the mathematical equations into a computer code file; and

6) providing the stand alone interface through which the user enters a requested memory device wherein the stand alone interface invokes the characteristic mathematical equations to provide the user the menu listing several configurations of the memory device which meets the user'"'"'s requirements.

2. The memory compiler methodlogy of claim 1 further comprising the substep of the stand alone memory interface generating software tool views based on the memory device selected by the user from the menu provided in step 6.

3. The memory compiler methodology of claim 1 further comprising the substep of the stand alone memory interface generating a physical data file of the memory device selected by the user from the menu provided in step 6.

4. The memory compiler methodology of claim 3 wherein the substep of the stand alone memory interface generating a physical data file further comprising the substeps of:

a) the stand alone memory interface invoking step 5 to generate the memory device selected by the user in step 6;

b) generating the memory array for the selected memory device;

c) generating the peripheral circuitry for the selected memory device; and

d) generating the power bus for the selected memory device.

5. In a memory compiler and method to provide a user specified memory device comprising the steps of:

1) precharacterizing a baseline configuration of the type of memory device from which all possible configurations are based on, to derive characteristic mathematical equations representing key parameters and properties of all possible valid configurations of the type of memory device; and

2) providing a stand alone memory interface through which a user specifies a memory device of a particular configuration and size wherein the stand alone memory interface invokes the characteristic mathematical equations of step

     1) to predict the key parameter values for each possible memory configuration that meets the requirements of the user specified memory device and provides a menu listing each possible memory configuration from which the user then chooses the configuration of the memory device that best meets his needs.

6. The memory compiler of claim 5 wherein the precharacterizing step further includes the steps of:

1a) initially designing the baseline configuration for the memory device;

1b) generating the transistor level circuitry for the various circuit blocks comprising the baseline configuration;

1c) generating a physical layout and X-Y coordinates to predetermined critical features of the physical layout for each of the various circuit blocks;

1d) converting the subsets 1a and 1b into computer code files;

1e) compiling all of the computer code files and verifying the functionality thereof across all architectural variables;

1f) selecting a small number of subsets of possible configurations of the memory device;

1g) statistically analyzing each of the subsets to derive characteristic mathematical equations based on a three variable analysis which represent key parameters and properties for all valid configurations of the memory device; and

1h) compiling all of the mathematical equations into a computer code file.

7. The memory compiler of claim 6 further comprising the substep of the stand alone memory interface generating software tool views based on the memory device selected by the user from the menu provided in step 2.

8. The memory compiler claim 7 further comprising the substep of the stand alone memory interface generating a physical data file of the memory device selected by the user from the menu provided in step 2.

9. The memory compiler of claim 8 wherein the substep of the stand alone memory interface generating a physical data file further comprises the substeps of:

a) the stand alone memory interface invoking substep 1h) to generate the memory device selected by the user in step 2;

b) generating the memory array for the selected memory device;

c) generating the peripheral circuitry for the selected memory device; and

d) generating the power bus for the selected memory device.