Method and apparatus for increasing data rates between nodes of a serial bus

• US 6,405,270 B1
• Filed: 09/08/1999
• Issued: 06/11/2002
• Est. Priority Date: 09/08/1999
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Chen, Dao-Long
• Primary Examiner(s): THAI, XUAN MARIAN
• Application Number:
  US09/392,039
• Time in Patent Office: 1,007 Days
• Field of Search: 710/100, 710/104, 713/1, 713/100, 370/256, 370/254, 370/255
• US Class Current: 710/104
• CPC Class Codes: H04L 12/40078 Bus configuration home automation networks H04L12/2803; arrangements for maintenance or administration H04L41/00
• CPC Class Codes: H04L 12/40123 Interconnection of computers and peripherals printer information exchange with computer G06F3/1293
• CPC Class Codes: H04L 12/44 Star or tree networks

Abstract

A method of altering topology of a serial bus having a plurality of nodes interconnected in a tree topology in order to increase data rates between the plurality of nodes includes the step of obtaining a current topology representation of the serial bus which indicates a first node of the plurality of nodes is coupled to a second node of the plurality of nodes via a third node of the plurality of nodes. Another step of the method includes obtaining data rate capabilities of each node of the serial bus. The method further includes determining based upon the current topology representation of the serial bus and the data rate capabilities of each node that the third node of supports a third maximum data rate that is slower than a first maximum data rate supported by the first node and a second maximum data rate supported by the second node. Furthermore, the method includes generating in response to the determining step a new topology representation for the serial bus in which the third node is not coupled between the first node and the second node.

Claims

1. A method of altering topology of a serial bus having a plurality of nodes interconnected in a tree topology in order to increase data rates between said plurality of nodes, comprising the computer-implemented steps of:

a) obtaining a current topology representation of said serial bus which indicates a first node of said plurality of nodes is coupled to a second node of said plurality of nodes via a third node of said plurality of nodes;

b) obtaining data rate capabilities of each node of said serial bus;

c) determining based upon said current topology representation of said serial bus and said data rate capabilities of each node that said third node of supports a third maximum data rate that is slower than a first maximum data rate supported by said first node and a second maximum data rate supported by said second node; and

d) generating in response to step (c), a new topology representation for said serial bus in which said third node is not coupled between said first node and said second node.

2. The method of claim 1, wherein:

step (c) further comprises the step of determining that said second node includes at least a first port and a second port, and

step (d) further comprises the step of generating said new topology representation such that said new topology representation indicates that said first node should be directly coupled to said first port of said second node and said third node should be directly coupled to said second port of said second node.

3. The method of claim 1, wherein:

step (c) further comprises the step of determining that said first node includes at least a first port and a second port, and

step (d) further comprises the step of generating said new topology representation such that said new topology representation indicates that said second node should be directly coupled to said first port of said first node and said third node should be directly coupled to said second port of said first node.

4. The method of claim 1, wherein step (d) further comprises the step of:

generating said new topology representation such that said new topology representation indicates that said third node should be directly coupled to a fourth node of said serial bus.

5. The method of claim 1, further comprising the step of receiving at least one user defined constraint for said tree topology of said serial bus, wherein step (d) further comprises the step of:

generating said new topology representation based upon said at least one user defined constraint.

6. The method of claim 1, further comprising the step of receiving at least one user defined constraint that indicates that said third node should be directly coupled to said second node, wherein:

step (c) further comprises the step of determining that said second node includes at least a first port and a second port, and

step (d) further comprises the step of generating said new topology representation such that said new topology representation indicates that said first node should be directly coupled to said first port of said second node and said third node should be directly coupled to said second port of second node.

7. A system for altering topology of a serial bus having a plurality of nodes interconnected in a tree topology in order to increase data rates between said plurality of nodes, comprising

a processor;

a serial bus adapter operable to provide said processor with an interface to said plurality of nodes; and

a memory comprising a plurality of instruction which when executed by said processor cause said processor to;

a) obtain a current topology representation of said serial bus via said serial bus adapter which indicates a first node of said plurality of nodes is coupled to a second node of said plurality of nodes via a third node of said plurality of nodes;

b) obtain data rate capabilities of each node of said serial bus via said serial bus adapter;

c) generate a new topology representation for said serial bus in which said third node is not coupled between said first node and said second node in response to determining based upon said current topology representation of said serial bus and said data rate capabilities of each node that said third node supports a third maximum data rate that is slower than a first maximum data rate supported by said first node and a second maximum data rate supported by said second node.

8. The system of claim 7, wherein said memory further includes instructions which when executed by said processor further cause said processor to:

determine that said second node includes at least a first port and a second port, and

generate said new topology representation such that said new topology representation indicates that said first node should be directly coupled to said first port of said second node and said third node should be directly coupled to said second port of said second node.

9. The system of claim 7, wherein said memory further includes instructions which when executed by said processor further cause said processor to:

determine that said first node includes at least a first port and a second port, and

generate said new topology representation such that said new topology representation indicates that said second node should be directly coupled to said first port of said first node and said third node should be directly coupled to said second port of said first node.

10. The system of claim 7, wherein said memory further includes instructions which when executed by said processor further cause said processor to:

generate said new topology representation such that said new topology representation indicates that said third node should be directly coupled to a fourth node of said serial bus.

11. The system of claim 7, wherein said memory further includes instruction which when executed by said processor further cause said processor to:

receive at least one user defined constraint for said tree topology of said serial bus, and

generate said new topology representation based upon said at least one user defined constraint.

12. The system of claim 7, wherein said memory further includes instructions which when executed by said processor further cause said processor to:

receive at least one user defined constraint that indicates that said third node should be directly coupled to said second node,

determine that said second node includes at least a first port and a second port, and

generate said new topology representation such that said new topology representation indicates that said first node should be directly coupled to said first port of said second node and said third node should be directly coupled to said second port of second node.

13. A computer readable medium for configuring a system for altering topology of a serial bus having a plurality of nodes interconnected in a tree topology in order to increase data rates between said plurality of nodes, comprising a plurality of instructions which when executed by said system cause said system to:

a) obtain a current topology representation of said serial bus which indicates a first node of said plurality of nodes is coupled to said second node of said plurality of nodes via a third node of said plurality of nodes;

b) obtain data rate capabilities of each node of said serial bus; and

c) generate a new topology representation for said serial bus in which said third node is not coupled between said first node and said second node in response to determining based upon said current topology representation and said data rate capabilities of each node that (i) said first node supports a first maximum data rate, (ii) said second node supports a second maximum data rate, and (iii) said third node of said serial bus supports a third maximum data rate that is slower than said first data rate and said second data rate.

14. The computer readable medium of claim 13, wherein said plurality of instructions when executed by said system further cause said system to:

determine that said second node includes at least a first port and a second port, and

generate said new topology representation such that said new topology representation indicates that said first node should be directly coupled to said first port of said second node and said third node should be directly coupled to said second port of said second node.

15. The computer readable medium of claim 13, wherein said plurality of instructions when executed by said system further cause said system to:

determine that said first node includes at least a first port and a second port, and

generate said new topology representation such that said new topology representation indicates that said second node should be directly coupled to said first port of said first node and said third node should be directly coupled to said second port of said first node.

16. The computer readable medium of claim 13, wherein said plurality of instructions when executed by said system further cause said system to:

generate said new topology representation such that said new topology representation indicates that said third node should be directly coupled to a fourth node of said serial bus.

17. The computer readable medium of claim 13, wherein said plurality of instructions when executed by said system further cause said system to:

receive at least one user defined constraint for said tree topology of said serial bus, and

generate said new topology representation based upon said at least one user defined constraint.

18. The computer readable medium of claim 13, wherein said plurality of instructions when executed by said system further cause said system to:

receive at least one user defined constraint that indicates that said third node should be directly coupled to said second node,

determine that said second node includes at least a first port and a second port, and

generate said new topology representation such that said new topology representation indicates that said first node should be directly coupled to said first port of said second node and said third node should be directly coupled to said second port of second node.