Asynchronous request/synchronous data dynamic random access memory
First Claim
1. A memory device having an array of memory cells, the memory device comprising:
- a selection circuit, including a register to store a value, wherein the selection circuit generates a mode selection signal based on the value stored the register;
a first buffer to receive an external signal and to output a buffered version of the external signal;
a second buffer to receive a clock enable signal, wherein in response to the clock enable signal, a control signal enables the first buffer;
a multiplexer coupled to the first buffer and the selection circuit, the multiplexer to select one of a plurality of clock signals in response to the mode selection signal, the plurality of clock signals including first and second clock signals; and
an output buffer coupled to the multiplexer, and the first buffer, to output data in response to the buffered version of the external signal, wherein, the output buffer outputs data in response to transitions of the first clock signal when the mode selection signal is in a first state and the output buffer outputs the data in response to transitions of the second clock signal when the mode selection signal is in a second state.
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Abstract
A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.
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Citations
51 Claims
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1. A memory device having an array of memory cells, the memory device comprising:
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a selection circuit, including a register to store a value, wherein the selection circuit generates a mode selection signal based on the value stored the register;
a first buffer to receive an external signal and to output a buffered version of the external signal;
a second buffer to receive a clock enable signal, wherein in response to the clock enable signal, a control signal enables the first buffer;
a multiplexer coupled to the first buffer and the selection circuit, the multiplexer to select one of a plurality of clock signals in response to the mode selection signal, the plurality of clock signals including first and second clock signals; and
an output buffer coupled to the multiplexer, and the first buffer, to output data in response to the buffered version of the external signal, wherein, the output buffer outputs data in response to transitions of the first clock signal when the mode selection signal is in a first state and the output buffer outputs the data in response to transitions of the second clock signal when the mode selection signal is in a second state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
a third buffer to receive a strobe signal; and
a plurality of input latches to sample address information upon detection of the strobe signal, wherein the address information specifies a storage location of the data.
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16. A method of controlling the operation of a memory device by a memory controller, the memory device having a multiplexer to select one of a plurality of clock signals in response to mode selection information, a buffer to receive an external signal and output a buffered version of the external signal, and a register to store the mode selection information, the method comprising:
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providing a clock enable signal to the memory device wherein, in response to the clock enable signal, the buffer is enabled;
providing the mode selection information to the memory device, the mode selection information specifying an operating mode selected from a plurality of operating modes to the memory device, the plurality of operating modes including first and second operating modes; and
providing a read command to the memory device wherein, in response to the read command, the memory device outputs data in response to the buffered version of the external signal, wherein the memory device outputs data in synchronism with a first clock signal of the plurality of clock signals when the mode selection information is indicative of the first operating mode, and the memory device outputs data in synchronism with a second clock signal of the plurality of clock signals when the mode selection information is indicative of the second operating mode. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. A method of operation in a memory device, the memory device having a multiplexer coupled to first and second clock lines to receive respective first and second clock signals, and a buffer to receive an external signal and to generate a buffered version of the external signal, wherein the first and second clock signals are derived from the external signal, the method of operation comprising:
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receiving a clock enable signal from a controller, wherein in response to the clock enable signal, the buffer is enabled;
generating the buffered version of the external signal when the buffer is enabled;
receiving mode selection information from a controller, the mode selection information specifying one of a plurality of operating modes including first and second operating modes;
coupling a control input of an output buffer to the buffer and one of the first and second clock lines using the multiplexer, the first clock line being coupled to the control input when the mode selection information specifies the first operating mode, and the second clock line being coupled to the control input when the mode selection information specifies the second operating mode; and
outputting data synchronously with respect to the first clock signal when the mode selection information specifies the first operating mode; and
outputting data synchronously with respect to the second clock signal when the mode selection information specifies the second operating mode. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37, 38, 39)
receiving a strobe signal; and
sampling address information upon detection of the strobe signal, wherein the address information identifies a storage location of the data output.
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38. The method of claim 30 further comprising receiving a timing mark that indicates when to begin outputting the data.
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39. The method of claim 38 wherein the timing mark is provided by a transition in the clock enable signal.
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40. An integrated circuit device comprising:
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a clock buffer to receive an external signal and to output a buffered version of the external signal;
a clock enable buffer to receive a clock enable signal, wherein in response to the clock enable signal, the clock buffer is enabled;
a register to store a value, wherein a mode selection signal is generated based on the value stored in the register;
a delay lock loop coupled to the clock buffer, the delay lock loop to receive an external clock signal and generate an internal clock signal;
a multiplexer to receive a mode selection signal, the multiplexer to select the internal clock signal when the mode selection signal specifies a first mode, and the multiplexer to select the external clock signal when the mode selection signal specifies a second mode; and
an output buffer, coupled to the multiplexer, and the clock buffer, to output data in response to the buffered version of the clock signal, wherein the data is output in synchronism with consecutive rising and falling edge transitions of the internal clock signal when the mode selection signal specifies the first mode, and wherein the data is output in synchronism with consecutive rising and falling edge transitions of the external clock signal when the mode selection signal specifies the second mode. - View Dependent Claims (41, 42, 43, 44, 45)
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46. A method of operation in a memory device having an array of memory cells, a register to store a value that is representative of an operating mode and a buffer that receives an external signal, wherein the buffer generates a buffered version of the external signal, the method comprising:
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generating a mode selection signal, wherein the mode selection signal is representative of the operating mode;
receiving a clock enable signal to enable the buffer;
selecting one of a plurality of clock signals in response to the mode selection signal, the plurality of clock signals including first and second clock signals; and
outputting data in response to the buffered version of the external signal, wherein the data is output in synchronism with transitions of the first clock signal when the mode selection signal is in a first state and, wherein the data is output in synchronism with transitions of the second clock signal when the mode select signal is in a second state. - View Dependent Claims (47, 48, 49, 50, 51)
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Specification