Asynchronous request/synchronous data dynamic random access memory

• US 6,405,296 B1
• Filed: 08/11/2000
• Issued: 06/11/2002
• Est. Priority Date: 05/07/1996
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Barth, Richard Maurice, Hampel, Craig Edward, Ware, Frederick Abbot, Horowitz, Mark Alan
• Primary Examiner(s): Ellis, Kevin L.
• Application Number:
  US09/638,302
• Time in Patent Office: 669 Days
• Field of Search: 711/104, 711/105, 711/167, 711/168, 711/169, 713/400, 713/401, 713/500, 713/501
• US Class Current: 711/167
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.

Claims

1. A memory device having an array of memory cells, the memory device comprising:

a selection circuit, including a register to store a value, wherein the selection circuit generates a mode selection signal based on the value stored the register;

a first buffer to receive an external signal and to output a buffered version of the external signal;

a second buffer to receive a clock enable signal, wherein in response to the clock enable signal, a control signal enables the first buffer;

a multiplexer coupled to the first buffer and the selection circuit, the multiplexer to select one of a plurality of clock signals in response to the mode selection signal, the plurality of clock signals including first and second clock signals; and

an output buffer coupled to the multiplexer, and the first buffer, to output data in response to the buffered version of the external signal, wherein, the output buffer outputs data in response to transitions of the first clock signal when the mode selection signal is in a first state and the output buffer outputs the data in response to transitions of the second clock signal when the mode selection signal is in a second state.

2. The memory device of claim 1 wherein the first state is indicative of a synchronous data transfer mode, and the second state is indicative of a slow synchronous data transfer mode.

3. The memory device of claim 2 wherein, in the synchronous data transfer mode, the outputting of data is synchronized with an output of a delay lock loop, and in the slow synchronous data transfer mode, the outputting of data is synchronized with an external clock signal.

4. The memory device of claim 1 further comprising a clock generation circuit to receive an external clock signal and generate the first clock signal using the external clock signal.

5. The memory device of claim 4 wherein the clock generation circuit includes a delay lock loop.

6. The memory device of claim 1 wherein the second clock signal is an external clock signal.

7. The memory device of claim 1 wherein the output buffer receives timing information from the control signal and, in response, begins outputting the data.

8. The memory device of claim 1 wherein the output buffer outputs the data in response to consecutive transitions of one of the first and second clock signals.

9. The memory device of claim 8 wherein the consecutive transitions include rising and falling edge transitions.

10. The memory device of claim 1 wherein the external signal is an external strobe signal, wherein the output buffer outputs the data in response to the external strobe signal when the mode selection signal is in a third state.

11. The memory device of claim 10 wherein the third state is indicative of an asynchronous data transfer mode.

12. The memory device of claim 10 wherein the external strobe signal is a column address strobe.

13. The memory device of claim 1 further comprising a delay lock loop, coupled to the first buffer, wherein the delay lock loop generates the first clock signal using the external signal.

14. The memory device of claim 1 wherein the second clock signal is the external signal.

15. The memory device of claim 1 further comprising:

a third buffer to receive a strobe signal; and

a plurality of input latches to sample address information upon detection of the strobe signal, wherein the address information specifies a storage location of the data.

16. A method of controlling the operation of a memory device by a memory controller, the memory device having a multiplexer to select one of a plurality of clock signals in response to mode selection information, a buffer to receive an external signal and output a buffered version of the external signal, and a register to store the mode selection information, the method comprising:

providing a clock enable signal to the memory device wherein, in response to the clock enable signal, the buffer is enabled;

providing the mode selection information to the memory device, the mode selection information specifying an operating mode selected from a plurality of operating modes to the memory device, the plurality of operating modes including first and second operating modes; and

providing a read command to the memory device wherein, in response to the read command, the memory device outputs data in response to the buffered version of the external signal, wherein the memory device outputs data in synchronism with a first clock signal of the plurality of clock signals when the mode selection information is indicative of the first operating mode, and the memory device outputs data in synchronism with a second clock signal of the plurality of clock signals when the mode selection information is indicative of the second operating mode.

17. The method of claim 16 wherein the first operating mode is a synchronous data transfer mode, and the second operating mode is a slow synchronous data transfer mode.

18. The method of claim 17 wherein, in the synchronous data transfer mode, the memory device synchronizes the outputting of data using a delay lock loop, and in the slow synchronous data transfer mode, the memory device synchronizes the outputting of data using an external clock signal.

19. The method of claim 16 wherein the second clock signal is an external clock signal.

20. The method of claim 16 wherein the plurality of operating modes further includes a third operating mode, and the memory device outputs the data in response to an external strobe signal when the mode selection information is indicative of the third operating mode.

21. The method of claim 20 wherein the third operating mode is an asynchronous data transfer mode.

22. The method of claim 16 wherein the external strobe signal is a column address strobe.

23. The method of claim 16 wherein the data is output on consecutive clock transitions of one of the plurality of clock signals selected in response to the mode selection information.

24. The method of claim 23 wherein the consecutive clock transitions include rising and falling edge transitions.

25. The method of claim 16 wherein the mode selection information is a binary value.

26. The method device of claim 16 further comprising providing a row address to the memory device, and providing a column address to the memory device, wherein the row and column address are multiplexed using an external strobe signal.

27. The method of claim 16 further comprising receiving the data output by the memory device.

28. The method of claim 16 further comprising sampling the data output by the memory device, wherein the data is sampled synchronously with respect to an external clock signal.

29. The method device of claim 16 further including providing timing information to the memory device, the timing information indicating to the memory device when to begin outputting the data.

30. A method of operation in a memory device, the memory device having a multiplexer coupled to first and second clock lines to receive respective first and second clock signals, and a buffer to receive an external signal and to generate a buffered version of the external signal, wherein the first and second clock signals are derived from the external signal, the method of operation comprising:

receiving a clock enable signal from a controller, wherein in response to the clock enable signal, the buffer is enabled;

generating the buffered version of the external signal when the buffer is enabled;

receiving mode selection information from a controller, the mode selection information specifying one of a plurality of operating modes including first and second operating modes;

coupling a control input of an output buffer to the buffer and one of the first and second clock lines using the multiplexer, the first clock line being coupled to the control input when the mode selection information specifies the first operating mode, and the second clock line being coupled to the control input when the mode selection information specifies the second operating mode; and

outputting data synchronously with respect to the first clock signal when the mode selection information specifies the first operating mode; and

outputting data synchronously with respect to the second clock signal when the mode selection information specifies the second operating mode.

31. The method of claim 30 wherein the data is output synchronously with respect to consecutive clock transitions of one of the first and second clock signals.

32. The method of claim 31 wherein the consecutive clock transitions include a rising edge transition and a falling edge transition.

33. The method of claim 30 wherein the plurality of operating modes further includes a third operating mode, the method further including outputting data in response to transitions of an external strobe signal when the mode selection signal specifies the third operating mode, wherein the external signal is the external strobe signal.

34. The method of claim 30 wherein the memory device generates the first clock signal using a delay lock loop, wherein the delay lock loop receives an external clock signal and the external signal is the external clock signal.

35. The method of claim 34 wherein the delay lock loop generates the first clock signal to have a predetermined timing relationship with an external clock signal.

36. The method of claim 30 further comprising receiving a read command, wherein the data is output in response to the read command after a number of clock cycles of the external clock signal transpire.

37. The method of claim 36 wherein receiving the read command comprises:

receiving a strobe signal; and

sampling address information upon detection of the strobe signal, wherein the address information identifies a storage location of the data output.

38. The method of claim 30 further comprising receiving a timing mark that indicates when to begin outputting the data.

39. The method of claim 38 wherein the timing mark is provided by a transition in the clock enable signal.

40. An integrated circuit device comprising:

a clock buffer to receive an external signal and to output a buffered version of the external signal;

a clock enable buffer to receive a clock enable signal, wherein in response to the clock enable signal, the clock buffer is enabled;

a register to store a value, wherein a mode selection signal is generated based on the value stored in the register;

a delay lock loop coupled to the clock buffer, the delay lock loop to receive an external clock signal and generate an internal clock signal;

a multiplexer to receive a mode selection signal, the multiplexer to select the internal clock signal when the mode selection signal specifies a first mode, and the multiplexer to select the external clock signal when the mode selection signal specifies a second mode; and

an output buffer, coupled to the multiplexer, and the clock buffer, to output data in response to the buffered version of the clock signal, wherein the data is output in synchronism with consecutive rising and falling edge transitions of the internal clock signal when the mode selection signal specifies the first mode, and wherein the data is output in synchronism with consecutive rising and falling edge transitions of the external clock signal when the mode selection signal specifies the second mode.

41. The integrated circuit device of claim 40 wherein the output buffer outputs data in synchronism with transitions of an external strobe signal when the mode selection signal specifies a third mode.

42. The integrated circuit device of claim 40 further including a flip flop coupled to the clock enable buffer, to receive a buffered version of the clock enable signal, wherein an output of the flip flop disables the clock buffer in response to a transisition in the clock enable signal.

43. The integrated circuit device of claim 40 further including an array of dynamic memory cells.

44. The integrated circuit device of claim 40 wherein the multiplexer is coupled to the delay lock loop to receive the internal clock signal, the multiplexer having an output signal line coupled to an input of the output buffer.

45. The integrated circuit device of claim 40 wherein the multiplexer provides the internal clock signal to a clock input of the output buffer when the mode selection signal specifies the first mode.

46. A method of operation in a memory device having an array of memory cells, a register to store a value that is representative of an operating mode and a buffer that receives an external signal, wherein the buffer generates a buffered version of the external signal, the method comprising:

generating a mode selection signal, wherein the mode selection signal is representative of the operating mode;

receiving a clock enable signal to enable the buffer;

selecting one of a plurality of clock signals in response to the mode selection signal, the plurality of clock signals including first and second clock signals; and

outputting data in response to the buffered version of the external signal, wherein the data is output in synchronism with transitions of the first clock signal when the mode selection signal is in a first state and, wherein the data is output in synchronism with transitions of the second clock signal when the mode select signal is in a second state.

47. The method of claim 46 wherein the first state is indicative of a synchronous data transfer mode, and the second state is indicative of a slow synchronous data transfer mode.

48. The method of claim 47 wherein, in the synchronous data transfer mode, the outputting of data is synchronized with respect to an output of a delay lock loop, and in the slow synchronous data transfer mode, the outputting of data is synchronized with respect to an external clock signal during the memory read transaction.

49. The method of claim 46 wherein the first clock signal is an output of a delay lock loop.

50. The method of claim 49 wherein the delay lock loop receives an external clock signal, and wherein the external signal is the external clock signal.

51. The method of claim 50 wherein the output buffer outputs the data in reference to consecutive rising and falling edge transitions of one of the first and second clock signals.