Defect management for interface to electrically-erasable programmable read-only memory

• US 6,405,323 B1
• Filed: 03/30/1999
• Issued: 06/11/2002
• Est. Priority Date: 03/30/1999
• Status: Expired due to Term

• Current Assignee: Greenliant LLC
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Xing, Dongsheng, Lin, Frank Fong-Long
• Primary Examiner(s): Iqbal, Nadeem
• Application Number:
  US09/281,357
• Time in Patent Office: 1,169 Days
• Field of Search: 714/8, 714/7-4, 714/2, 714/13, 714/25, 714/30, 714/31, 714/39, 714/42, 714/44, 711/103, 711/104, 711/152
• US Class Current: 714/6.13
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/88 with partially good memories

Abstract

A circuit interfaces a host processor to an electrically-erasable memory in a memory space, such as a flash media. The memory space defines a plurality of segments, and each of the segments includes a plurality of sectors. A media interface circuit regulates access by the host processor to the electrically-erasable memory in the memory space. Sector valid indication reading circuitry reads at least one sector valid indication from a segment of the media. Sector valid determination circuitry determines a non-defective sector from the at least one sector valid indication read. Sector level segment defect map indication reading circuitry reads a sector-level segment defect map from the sector determined to be non-defective. Sector defect determination circuitry determines, from the sector-level segment defect map read, sectors within the segment that are valid. Access regulation circuitry regulates access to the memory space at least in part on the determinations by the sector defect determination circuitry.

Claims

1. A system to interface a host processor to an electrically-erasable memory in a memory space, the memory space defining a plurality of segments and each of the segments including a plurality of sectors, including:

media interface means that regulates access by the host processor to the electrically-erasable memory in the memory space;

sector valid indication reading means to read at least one sector valid indication from a segment of the media;

sector valid determination means to determine a non-defective sector from the at least one sector valid indication read;

sector level segment defect map indication reading means to read a sector-level segment defect map from the sector determined to be non-defective;

sector defect determination means to determine, from the sector-level segment defect map read, sectors within the segment that are valid;

access regulation means to regulate access to the memory space at least in part on the determinations by the sector defect determination means.

2. The interface system of claim 1, wherein the access regulation means prohibits access to a particular sector when a portion of the sector-level segment defect map indicates that the particular sector is not valid.

3. The interface system of claim 1, and further including controlling means to control the segment defect map indication reading means such that the only segment defect map read by the segment defect map indication reading means for a particular segment is a segment defect map determined first by the segment defect map validation means to be valid.

4. The interface system of claim 1, wherein each segment defect map includes a plurality of bits, and each bit of the segment defect map corresponds to a separate sector of that segment.

5. The interface system of claim 1, wherein each segment defect map includes a plurality of bits, and each bit corresponds to a plurality of sectors of the particular segment.

6. The interface system of claim 1, wherein when a portion of the media where a particular sector valid indication is stored is defective, the sector valid determination means provides a determination in response thereto that the sector corresponding to the particular sector valid indication is also defective, such that the segment defect map stored in that sector is considered by the sector level segment defect map indication reading means to be defective.

9. The interface method of claim 6, and further including a controlling step to control the segment defect map indication reading step such that the only segment defect map read in the segment defect map indication reading step for a particular segment is a segment defect map determined first in the segment defect map validation step to be valid.

10. The interface system of claim 6, wherein each segment defect map includes a plurality of bits, and each bit of the segment defect map corresponds to a separate sector of that segment.

11. The interface system of claim 6, wherein each segment defect map includes a plurality of bits, and each bit corresponds to a plurality of sectors of the particular segment.

12. The interface system of claim 6, wherein when a portion of the media where a particular sector valid indication is stored is defective, the sector valid determination step provides a determination in response thereto that the sector corresponding to the particular sector valid indication is also defective, such that the segment defect map stored in that sector is considered by the sector level segment defect map indication reading step to be defective.

7. A method to interface a host processor to an electrically-erasable memory in a memory space, the memory space defining a plurality of segments and each of the segments including a plurality of sectors, including:

regulating access by the host processor to the electrically-erasable memory in the memory space;

reading at least one sector valid indication from a segment of the media;

determining a non-defective sector from the at least one sector valid indication read;

reading a sector-level segment defect map from the sector determined to be non-defective;

determining, from the sector-level segment defect map read, sectors within the segment that are valid;

wherein the step of regulating access operates at least in part on the determinations in the sector defect determination step.

8. The interface method of claim 7, wherein the access regulation step prohibits access to a particular sector when a portion of the sector-level segment defect map indicates that the particular sector is not valid.

13. A method for tracking defective segments of an electrically-erasable read-only memory in a memory space, the memory space defining a plurality of segments, including:

reading a manufacture defect list, the manufacture defect list being an indication of one or more first segments that cannot be written during a low-level format of the memory;

creating a hard defect table from the manufacture defect list to indicate the first segments of the memory are unusable;

attempting to erase a second segment of the memory and determining whether the erasure is a failure;

modifying the hard defect table to also indicate one or more second segments of the memory, that are not one of the first segments, is unusable based on the determination that the erasure of the second segment is a failure,

wherein access to the memory is based at least in part on the hard defect table.

14. The method of claim 13, and further including:

before the erase attempting step, determining whether the second segment has been marked as being erasable;

wherein only segment segments determined to be erasable are attempted to be erased in the erase attempting step.

15. The method of claim 14, and further including:

before the hard defect table modifying step, marking the second segment as being erasable.

16. A system that tracks defective segments of an electrically-erasable read-only memory in a memory space, the memory space defining a plurality of segments, including:

means for reading a manufacture defect list, the manufacture defect list being an indication of one or more first segments that cannot be written during a low-level format of the memory;

means for creating a hard defect table from the manufacture defect list to indicate the first segments of the memory are unusable;

means for attempting to erase a second segment of the memory and determining whether the erasure is a failure;

means for modifying the hard defect table to also indicate one or more second segments of the memory, that are not one of the first segments, is unusable based on the determination that the erasure of the second segment is a failure,

wherein access to the memory is based at least in part on the hard defect table.

17. The system of claim 16, and further including:

means for determining whether the second segment has been marked as being erasable, wherein the erase attempting means only attempts to erase;

wherein only segment segments determined to be erasable are attempted to be erased by the erase attempting means.

18. The system of claim 17, and further including:

means for marking the second segment as being erasable before modifying the hard defect table.

19. A memory system for use by a host processor, including:

electrically erasable memory addressable by the host processor in the memory space of the host processor, the memory space defining a plurality of segments and each of the segments including a plurality of sectors;

media interface means that regulates access by the host processor to the electrically-erasable memory in the memory space;

sector valid indication reading means to read at least one sector valid indication from a segment of the media;

sector valid determination means to determine a non-defective sector from the at least one sector valid indication read;

sector level segment defect map indication reading means to read a sector-level segment defect map from the sector determined to be non-defective;

sector defect determination means to determine, from the sector-level segment defect map read, sectors within the segment that are valid;

access regulation means to regulate access to the memory space at least in part on the determinations by the sector defect determination means.

20. The memory system of claim 19, wherein the access regulation means prohibits access to a particular sector when a portion of the sector-level segment defect map indicates that the particular sector is not valid.

21. The memory of claim 19, and further including controlling means to control the segment defect map indication reading means such that the only segment defect map read by the segment defect map indication reading means for a particular segment is a segment defect map determined first by the segment defect map validation means to be valid.

22. The memory system of claim 19, wherein each segment defect map includes a plurality of bits, and each bit of the segment defect map corresponds to a separate sector of that segment.

23. The memory system of claim 19, wherein each segment defect map includes a plurality of bits, and each bit corresponds to a plurality of sectors of the particular segment.

24. The memory system of claim 19, wherein when a portion of the media where a particular sector valid indication is stored is defective, the sector valid determination means provides a determination in response thereto that the sector corresponding to the particular sector valid indication is also defective, such that the segment defect map stored in that sector is considered by the sector level segment defect map indication reading means to be defective.