Deep sub-micron static timing analysis in the presence of crosstalk

• US 6,405,348 B1
• Filed: 01/11/2000
• Issued: 06/11/2002
• Est. Priority Date: 10/27/1999
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Fallah-Tehrani, Peivand, Chyou, Shang-Woo
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US09/481,750
• Time in Patent Office: 882 Days
• Field of Search: 716/4, 716/5, 716/6
• US Class Current: 716/113
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A method for static timing analysis of deep sub-micron devices in presence of crosstalk. The present invention provides an efficient platform for fast and accurate static timing verification of large scale transistor and cell level netlists, with coupled interconnects and high switching speeds. The present invention also provides a novel approach to solve the coupled noise problem in static timing verification. The present invention also provides for a method of determining worst case aggressor switching time for a cross-coupled interconnect stage. After the worst case aggressor switching time is determined, the netlist is then resimulated using the worst case aggressor switching time to determine more accuate stage delay and slew of the interconnect stage. The output waveform is recorded and utilized as the input of subsequent stages.

Claims

1. In a computer system, a method of analysing crosstalk effects on interconnects of an integrated circuit design represented as a netlist, the method comprising the steps of:

a) accessing a netlist and identifying a cross-coupled circuit contained therein, wherein said cross-coupled circuit includes a primary net and an aggressor net;

b) generating a primary waveform of said cross-coupled circuit;

c) generating a bump-envelope waveform of said cross-coupled circuit;

d) super-positioning said primary waveform over said bump-envelope waveform to generate a composite waveform;

e) determining a threshold voltage crossing point of said composite waveform; and

f) determining a worst case aggressor switching time based on said threshold voltage crossing point.

2. A method as recited in claim 1 further comprising the steps of:

generating an output waveform by re-simulating said cross-coupled circuit with said worst case aggressor switching time; and

determining a non-linear worst case delay of said output waveform.

3. A method as recited in claim 2 further comprising the step of determining a slew of said output waveform.

4. A method as recited in claim 3 further comprising the step of generating a path timing report containing said non-linear worst case delay and said slew.

5. A method as recited in claim 1 wherein said step (b) comprises the step of switching an input of said primary net.

6. A method as recited in claim 1 wherein said step (c) comprises the steps of:

generating a bump waveform by switching an input of said aggressor net; and

forming said bump-envelope waveform by stretching said bump waveform along a predetermined aggressor switching window.

7. A method as recited in claim 5 wherein said step (f) comprises the steps of:

determining a time delay required for said bump waveform to reach a peak voltage; and

determining said worst case switching time by substracting said time delay from said threshold voltage crossing point.

8. A computer-readable medium having contained therein computer-readable codes for causing a computer-implemented electronics design automatic (EDA) to perform a method of analysing crosstalk effects on interconnects of an integrated circuit design represented as a netlist, the method comprising the steps of:

a) accessing a netlist and identifying a cross-coupled circuit contained therein, wherein said cross-coupled circuit includes a primary net and an aggressor net;

b) generating a primary waveform for said cross-coupled circuit;

c) generating a bump-envelope waveform of said cross-coupled circuit;

d) super-positioning said primary waveform over said bump-envelope waveform to generate a composite waveform;

e) determining a threshold voltage crossing point of said composite waveform; and

f) determining a worst case aggressor switching time based on said threshold voltage crossing point.

9. A computer-readable medium as recited in claim 8 wherein said method further comprises the steps of:

generating an output waveform by re-simulating said cross-coupled circuit with said worst case aggressor switching time; and

determining a non-linear worst case delay of said output waveform.

10. A computer-readable medium as recited in claim 9 wherein said method further comprises the step of determining a slew of said output waveform.

11. A computer-readable medium as recited in claim 10 wherein said method further comprises the step of generating a path timing report containing said non-linear worst case delay and said slew.

12. A computer-readable medium as recited in claim 8 wherein said step (b) of said method comprises the step of switching an input of said primary net.

13. A computer-readable medium as recited in claim 8 wherein said step (c) of said method comprises the steps of:

generating a bump waveform by switching an input of said aggressor net; and

forming said bump-envelope waveform by stretching said bump waveform along a predetermined aggressor switching window.

14. A computer-readable medium as recited in claim 13 wherein said step (f) of said method further comprises the steps of:

determining a time delay required for said bump waveform to reach a peak voltage; and

determining said worst case switching time by substracting said time delay from said threshold voltage crossing point.

15. A computer-implemented electronics design automation (EDA) system comprising:

means for accessing a netlist representative of an integrated circuit design;

means for identifying a cross-coupled circuit contained within said netlist, wherein said cross-coupled circuit includes a primary net and an aggressor net;

first simulation means for generating a primary waveform of said cross-coupled circuit;

second simulation means for generating a bump-envelope waveform of said cross-coupled circuit;

means for super-positioning said primary waveform over said bump-envelope waveform to generate a composite waveform;

first calculation means for determining a threshold voltage crossing point of said composite waveform; and

second calculation means for determining a worst case aggressor switching time based on said threshold voltage crossing point.

16. A system as recited in claim 15 further comprising:

means for generating an output waveform by re-simulating said cross-coupled circuit with said worst case aggressor switching time; and

means for determining a non-linear worst case delay of said output waveform.

17. A system as recited in claim 16 further comprising means for determining a slew of said output waveform.

18. A system as recited in claim 17 further comprising means for generating a path timing report containing said non-linear worst case delay and said slew.

19. A system as recited in claim 15 wherein said first simulation means comprises means for switching an input of said primary net.

20. A system as recited in claim 15 wherein said second simulation means comprises:

means for generating a bump waveform by switching an input of said aggressor net; and

means for forming said bump-envelope waveform by stretching said bump waveform along a predetermined aggressor switching window.

21. A system as recited in claim 20 wherein said second calculation means comprises:

means for determining a time delay required for said bump waveform to reach a peak voltage; and

means for determining said worst case switching time by substracting said time delay from said threshold voltage crossing point.

22. In a computer system, a method of analysing crosstalk effects on interconnects of an integrated circuit design represented as a netlist, the method comprising the steps of:

a) accessing a netlist and identifying a cross-coupled circuit contained therein, wherein said cross-coupled circuit includes a primary net and a plurality of aggressor nets;

b) generating a primary waveform of said cross-coupled circuit;

c) generating bump-envelope waveforms of said cross-coupled circuit;

d) generating an accumulative bump-envelope by super-positioning said bump-envelope waveforms;

e) super-positioning said primary waveform over said accumulative bump-envelope to generate a composite waveform;

f) determining a threshold voltage crossing point of said composite waveform; and

g) determining a plurality of worst case aggressor switching times each corresponding to a respective one of said plurality of aggressor nets based on said threshold voltage crossing point.

23. A method as recited in claim 22 further comprising the steps of:

generating an output waveform by re-simulating said cross-coupled circuit with said plurality of worst case aggressor switching times; and

determining a non-linear worst case delay of said output waveform.

24. A method as recited in claim 22 further comprising the step of determining a slew of said output waveform.

25. A method as recited in claim 24 further comprising the step of generating a path timing report containing said non-linear worst case delay and said slew.

26. A method as recited in claim 22 wherein said step (b) comprises the step of switching an input of said primary net.

27. A method as recited in claim 22 wherein said step (c) comprises the steps of:

generating a respective bump waveform by switching an input of one of said plurality aggressor nets; and

forming one of said plurality of bump-envelope waveforms by stretching said respective bump waveform along a predetermined aggressor switching window.

28. A method as recited in claim 27 wherein said step (g) comprises the steps of:

determining a time delay required for said respective bump waveform to reach a peak voltage; and

determining a respective one of said worst case switching times by substracting said time delay from said threshold voltage crossing point.