Vertical trench-formed dual-gate FET device structure and method for creation

• US 6,406,962 B1
• Filed: 01/17/2001
• Issued: 06/18/2002
• Est. Priority Date: 01/17/2001
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Nowak, Edward J., Divakaruni, Ramachandra, Rankin, Jed H., Ballantine, Arne W., Agnello, Paul D., Jones, Erin C.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Roman, Angel
• Application Number:
  US09/761,931
• Time in Patent Office: 517 Days
• Field of Search: 438/156, 438/157, 438/268, 438/269, 438/270, 438/272, 438/282, 438/284, 438/970
• US Class Current: 438/268
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel

Abstract

The present invention relates to an apparatus and method of forming one or more FETs having a vertical trench-formed double-gate, with a plurality of nitride layers having oxide marker etch-stop layers provided periodically there-through, thereby adapting the FETs to have a plurality of selectable gate lengths. The present invention provides for control and formation of gate lengths scaled down to about 5 nm to about 100 nm, preferably from about 5 nm to about 50 nm. The plurality of pad nitride layers with the oxide etch-stop layers provide for the present FET to be connected to a plurality of contacts having a variety of connection depths corresponding to the gate lengths used, by etching a plurality of via in the pad nitride layers whereby such vias stop at selected ones of the etch-stop layers to provide vias adapted to connect with the selected ones of such contacts. Additional gate material may be deposited over a top surface of the selected plurality of nitride layers to allow for contacts to the gate electrodes of any given FET.

Claims

1. A method of forming a FET comprising:

providing a substrate having a pad layer thereover, said pad layer having a plurality of etch stop layers periodically therethrough;

forming a plurality of openings adapted to connect with a plurality of contacts having varying dimensions wherein selected ones of said plurality of openings traverse through said pad layers and said plurality of etch stop layers, while still others of said plurality of openings traverse through said pad layer stopping at a selected one of said plurality of etch stop layers;

forming a vertical channel in one of said selected ones of said plurality of openings traversing through said pad layers and said plurality of etch stop layers;

forming first and second gates in said vertical channel; and

connecting said plurality of contacts to said substrate whereby at least one of said contacts connects to said vertical channel, while at least one of said contacts connects to one of said selected ones of said plurality of openings traverse through said pad layers and said plurality of etch stop layers, while still other contacts connect to said first and second gates, thereby providing a vertical gate FET having the plurality of contacts with varying depths.

2. The method according to claim 1 further including providing source and drain regions to said substrate.

3. The method according to claim 2 wherein said source and drain regions are provided in said selected ones of said plurality of openings traversing through said pad layers and said plurality of etch stop layers.

4. The method according to claim 1 wherein said substrate comprises a silicon on insulator, silicon on sapphire, or bulk silicon wafer.

5. The method according to claim 1 wherein said plurality of etch stop layers are deposited equidistantly during deposition of said pad layer.

6. The method according to claim 1 wherein said plurality of etch stop layers are deposited at varying depths during deposition of said pad layer.

7. The method according to claim 1 wherein said vertical gate FET comprises a first vertical gate FET having the plurality of contacts with varying depths connected to a die, said die having thereon at least a second vertical gate FET made by the process of claim 1 wherein a gate length of said second vertical gate FET and a gate length of said first vertical gate FET are different.

8. A method of forming a FET comprising:

providing a substrate having an active region;

providing a pad layer over said substrate, said pad layer having a plurality of etch stop layers;

forming a vertical channel traversing through said pad layer and said plurality of etch stop layers;

forming first and second gates in said vertical channel;

providing a plurality of contacts having varying depths;

forming a plurality of openings in said substrate adapted to connect with selected ones of said plurality of contacts having varying dimensions, wherein a first opening of said plurality of openings traverses said substrate connecting to said vertical channel, a second opening of said plurality of openings traverses said substrate connecting to said active region, while still other openings traverse through said pad layer of said substrate stopping at a selected one of said plurality of etch stop layers;

extending said first and second gates over a surface of said openings stopping at selected ones of said plurality of etch stop layers; and

connecting said plurality of contacts to said substrate whereby at least a first contact of said plurality of contacts connects to said first opening connecting to said vertical channel, at least a second contact of said plurality of contacts connects to said second opening connecting to said active region, while still others of said plurality of contacts connect to said first and second extended gates over said openings stopping at selected ones of said plurality of etch stop layers, thereby providing a vertical gate FET having the plurality of contacts with varying depths.

9. The method according to claim 8 wherein said substrate comprises a silicon on insulator, silicon on sapphire, or bulk silicon wafer.

10. The method according to claim 8 wherein said pad layer comprises a first pad layer and a second pad layer.

11. The method according to claim 10 wherein said first pad layer comprises an oxide layer.

12. The method according to claim 10 wherein said second pad layer comprises a nitride layer.

13. The method according to claim 8 wherein said plurality of etch stop layers comprise a plurality of oxide etch stop layers.

14. The method according to claim 8 wherein said vertical channel in said trench is formed by growing an underlying portion of a conductive layer of said substrate.

15. The method according to claim 8 wherein said first and second gates are extended by depositing additional gate material over the surface of the openings stopping at selected ones of the plurality of etch stop layers.

16. A method of forming a vertical multi-gate FET comprising:

providing a substrate having an active semiconductor layer;

providing a first pad layer thereover said substrate;

providing a second pad layer having a plurality of etch stop layers over said first pad layer;

forming a vertical trench traversing through said first and second pad layers and said plurality of etch stop layers stopping at a surface of said active semiconductor layer of said substrate;

forming a vertical channel in said vertical trench by growing said active semiconductor layer;

forming first and second vertical gates in said vertical channel;

providing a plurality of contacts having varying depths;

forming a plurality of openings adapted to connect with said plurality of contacts having varying dimensions wherein at least one of said openings traverses through said first and second pad layers stopping at said active semiconductor layer, while other openings traverse through said second pad layer stopping at a selected one of said plurality of etch stop layers having a depth corresponding to a depth of at least one of said contacts having varying depths;

providing additional gate material over said selected one of said plurality of etch stop layers to horizontally extend said first and second vertical gates; and

connecting said plurality of contacts having varying depths to said substrate whereby at least one of said contacts connects to said vertical channel, while at least one of said contacts connects to said active semiconductor layer, while still others connect to said first and second vertical gates, thereby providing a vertical double gate FET connected to the plurality of contacts having varying depths.

17. The method according to claim 16 wherein said semiconductor layer comprises a conductive material selected from the group consisting of silicon, silicon germanium, silicide, and titanium silicide.

18. The method according to claim 16 wherein said first pad layer is deposited to a thickness ranging from about 30 A to about 300 A.

19. The method according to claim 16 wherein said first pad layer comprises a pad oxide layer deposited by CVD to a thickness ranging from about 30 A to about 300 A.

20. The method according to claim 16 wherein said first pad layer further comprises a plurality of etch stop layers deposited periodically during deposition of said first pad layer.

21. The method according to claim 20 wherein said first pad layer having said plurality of etch stop layers comprises a pad oxide layer having a plurality of nitride etch stop layers deposited periodically during deposition of said pad oxide layer.

22. The method according to claim 21 wherein said pad oxide layer with the plurality of nitride etch stop layers is deposited to a combined thickness of about 2000 A with said plurality of nitride etch stop layers deposited to a thickness of about 10 A about every 200 A of said pad oxide layer deposition.

23. The method according to claim 16 wherein said second pad layer is deposited to a thickness ranging from about 800 A to about 10,000 A.

24. The method according to claim 16 wherein said second pad layer comprises a nitride layer deposited by nitridization or CVD to a thickness ranging from about 800 A to about 10,000 A.

25. The method according to claim 24 wherein said nitride layers comprise silicon nitride layers.

26. The method according to claim 16 wherein said second pad layer comprises a pad nitride layer having oxide etch stop layers wherein said oxide etch stop layers are deposited periodically during the pad nitride layer deposition for adapting said substrate to be connected to said plurality of contacts having varying depths.

27. The method according to claim 26 wherein said oxide etch stop layers comprise silicon dioxide.

28. The method according to claim 16 wherein said etch stop layers are deposited to a thickness ranging from about 5 A to about 50 A.

29. The method according to claim 16 wherein said gate material is a conductive material selected from the group consisting of polysilicon, titanium, tungsten aluminum, and gold.

30. The method according to claim 16 wherein said first and second gates have a thickness ranging from about 5 nm to about 100 nm.

31. The method according to claim 16 wherein the steps of forming said vertical channel comprises:

a) forming said trench by etching a top surface of said second pad layer stopping at a top surface of said first pad layer;

b) providing a conformal layer over a surface of said substrate thereby at least coating said trench with said conformal layer;

c) depositing a filler material over said substrate to at least filling remaining portions of said trench;

d) forming at least first and second spacers by etching said conformal layer;

e) exposing a portion of said active semiconductor layer by etching said filler material and any underlying first pad layer; and

f) forming said vertical channel by epitaxially growing said exposed portion of said active semiconductor layer.

32. The method according to claim 31 wherein said conformal layer is an insulating material selected from the group consisting of ASG, BPSG, PSG, and combinations thereof.

33. The method according to claim 31 wherein said conformal layer is deposited to a thickness ranging from about 200 A to about 2000 A.

34. The method according to claim 31 wherein said filler material is polysilicon, carbon, germanium oxide, germanium nitride, TiO₂, or combinations thereof.

35. The method according to claim 31 wherein said active semiconductor layer comprises a silicide disposed upon silicon, said step g) further comprises over-etching said substrate down to an active silicon layer of said substrate wherein said active silicon layer acts as a seed layer for subsequent epitaxial growth.

36. The method according to claim 31 wherein said steps of forming said first and second spacers by etching said conformal layer said step (d) further forms an isolation region.

37. The method according to claim 36 further including the step of filling said isolation region with an isolation material thereby separating said vertical double gate FET from adjacent FETs on a single die.

38. The method according to claim 37 wherein said isolation material is silicon dioxide or BPSG.

39. The method according to claim 31 wherein the steps of forming said first and second vertical gates comprise:

g) forming conductor holes by patterning and etching said first and second spacers to expose an underlying portion of said first pad layer;

h) forming thin diffusion regions in said conductor holes by growing said exposed first pad layer to at least fill a portion of said conductor holes; and

i) form said first and second gates by providing a gate material over said substrate thereby filling remaining portions of said conductor holes.

40. A method of making a die having multiple FETs with varying gate lengths comprising:

providing a die;

providing a first FET having a first gate length over said die whereby said FET is made by the steps of;

a) providing a substrate having an active layer;

b) providing a pad layer having a plurality of etch stop layers periodically therethrough over said substrate;

c) providing a plurality of contacts having varying dimensions;

d) forming a plurality of openings adapted to connect with said plurality of contacts having varying dimensions wherein at least first and second openings traverse through said pad layers and said plurality of etch stop layers, while other openings traverse through said pad layer stopping at selected ones of said plurality of etch stop layers;

e) forming a vertical channel in said first opening traversing through said pad layers and said plurality of etch stop layers;

f) forming at least first and second vertical gates in said vertical channel; and

g) connecting said plurality of contacts to said substrate whereby at least one of said contacts connects to said vertical channel, while at least another of said contacts connects to said second opening traversing through said pad layers and said plurality of etch stop layers, while still other contacts connect to said first and second gates, thereby providing said first FET having said first gate length; and

repeating steps a) through g) to provide a plurality of FETs having differing gate lengths over said die.