Wafer level packaging

• US 6,407,333 B1
• Filed: 11/04/1997
• Issued: 06/18/2002
• Est. Priority Date: 11/04/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Schroen, Walter H.
• Primary Examiner(s): Louis-Jacques, Jacques H.
• Assistant Examiner(s): MANCHO, RONNIE M
• Application Number:
  US08/963,769
• Time in Patent Office: 1,687 Days
• Field of Search: 174/52.2, 174/52.3, 174/52.4, 257/673, 257/691, 257/693, 257/735, 257/666, 298/25, 298/27, 298/30--38, 298/41, 298/46
• US Class Current: 174/529
• CPC Class Codes: H01L 2224/32014 the layer connector being smaller than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/20752 : larger or equal to 20 microns less than 30 microns
• CPC Class Codes: H01L 2924/20753 : larger or equal to 30 microns less than 40 microns
• CPC Class Codes: Y10T 29/49117 : Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49121 : Beam lead frame or beam lead device
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49131 : by utilizing optical sighting device
• CPC Class Codes: Y10T 29/49133 : with component orienting
• CPC Class Codes: Y10T 29/49135 : and shaping, e.g., cutting or bending, etc.
• CPC Class Codes: Y10T 29/49137 : Different components
• CPC Class Codes: Y10T 29/49139 : by inserting component lead or terminal into base aperture
• CPC Class Codes: Y10T 29/4914 : with deforming of lead or terminal
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base

Abstract

An integrated circuit package (50) may include an integrated circuit chip (22) having an integrated circuit (14). A lead frame (28) may be opposite the integrated circuit chip (22). The lead frame (28) may include at least one lead (30) electrically coupled to the integrated circuit (14) by a connector (42). The lead (30) may be within a periphery (32) of the integrated circuit chip (22). An encapsulant (44) may cover the integrated circuit (14), the connector (42) and a portion of the lead frame (28). A remaining portion of the lead frame (28) may be exposed from the encapsulant (44).

Claims

1. An integrated circuit device made by the process comprising:

providing a semiconductor wafer having a plurality of integrated circuits formed on a first side thereof;

disposing a strip of lead frames having a plurality of lead frames on said first side of said wafer so that each lead frame is aligned with one of said plurality of integrated circuits, each lead frame being entirely within a periphery of an area of said wafer along which said wafer will be separated to form a respective integrated circuit device;

electrically coupling each lead frame to said respective integrated circuit;

encapsulating said semiconductor wafer, with said lead frames attached, in its entirety, said encapsulant covering said first side and having an upper side which is opposite said first side but not in contact thereto, a portion of each of said lead frames being exposed along said upper side;

separating said wafer along said periphery to produce individual integrated circuit devices, side walls of said integrated circuit devices produced by said separation step being substantially perpendicular to said first side of said wafer, whereby no portion of said lead frame protrudes beyond said side walls of said individual integrated circuit devices.

2. The integrated circuit device of claim 1 wherein the lead frame includes a plurality of leads, and a securing agent securing said leads to said surface.

3. The integrated circuit device of claim 2, wherein said securing agent is electrically insulating and spaces said leads from said surface.

4. The integrated circuit device of claim 2, wherein the connector is wire bonded to the lead and to the integrated circuit.

5. The integrated circuit device of claim 2, further comprising:

a bonding pad electrically coupled to the integrated circuit;

the bonding pad disposed proximate to a centerline of the integrated circuit; and

the connector being a wire bonded to the lead and to the bonding pad.

6. The integrated circuit device of claim 2, wherein the lead is plated with palladium.

7.A packaged semiconductor wafer comprising:

a semiconductor wafer having a plurality of integrated circuits formed on a first side thereof;

a strip of lead frames having a plurality of lead frames disposed on said first side of said wafer so that each lead frame is aligned with one of said plurality of integrated circuits, each lead frame being entirely within a periphery of an area of said wafer along which said wafer will be separated to form a respective integrated circuit device;

each lead frame being electrically coupled to said respective integrated circuit;

said semiconductor wafer being encapsulated, with said lead frames attached, in its entirety, said encapsulant covering said first side and having an upper side which is opposite said first side but not in contact thereto, a portion of each of said lead frames being exposed along said upper side, whereby separation of said wafer along said periphery produces individual packaged integrated circuit devices.

7. The packaged wafer of claim 7, wherein the sheet of lead frames is a unitary sheet of material.

8. The packaged wafer of claim 8 wherein the lead frames further comprise a plurality of leads, and a securing agent securing said leads to said surface.

9. A packaged semiconductor wafer, comprising:

a plurality of integrated circuit on said wafer, each having a surface;

each integrated circuit including bonding pads on said surface and a periphery along which said wafer will be separated to form respective integrated circuit devices;

a strip of lead frames having a plurality of lead frames, opposite the surface of each of said integrated circuits and supported on said surfaces;

each lead frame of said strip of lead frames including a lead electrically coupled to a bonding pad of an associated said integrated circuit by a conductor;

each lead frame of said strip of lead frames disposed within said periphery of the associated integrated circuit;

an encapsulant covering each of the integrated circuits, the conductors and a portion of each lead frame; and

a remaining portion of each lead frame of said strip of lead frames exposed external to the encapsulant;

wherein a distal end of each said lead of each said lead frame of said strip of lead frames is substantially parallel to said surface.

10. The packaged wafer of claim 10, wherein each connector is a wire bonded to the lead and to the opposing integrated circuit.

11. The packaged wafer of claim 10, further comprising:

a bonding pad electrically coupled to each of the integrated circuits;

the bonding pad disposed proximate to a centerline of the integrated circuit; and

the connector being a wire bonded to the lead and to the bonding pad.

12. The packaged wafer of claim 10, wherein the lead is plated with palladium.

13. The packaged wafer of claim 10 further comprising an electrically insulating securing agent securing said leads to said surface and spacing said leads from said surface.