Multilayer dielectric stack and method

• US 6,407,435 B1
• Filed: 02/11/2000
• Issued: 06/18/2002
• Est. Priority Date: 02/11/2000
• Status: Expired due to Term

• Current Assignee: Sharp Laboratories of America Incorporated (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Laboratories of America Incorporated (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Ma, Yanjun, Ono, Yoshi
• Primary Examiner(s): Eckert, II, George C.
• Application Number:
  US09/502,420
• Time in Patent Office: 858 Days
• Field of Search: 257/405, 257/406, 257/410, 257/411, 438/216, 438/261, 438/288, 438/591
• US Class Current: 257/411
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts

Abstract

A multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material. The presence of the interposing material and the thinness of the high-k material layers reduces or eliminate effects of crystallization within the high-k material, even at relatively high annealing temperatures. The high-k dielectric layers are a metal oxide of preferably zirconium or hafnium. The interposing layers are preferably amorphous aluminum oxide, aluminum nitride, or silicon nitride. Because the layers reduce the effects of crystalline structures within individual layers, the overall tunneling current is reduced. Also provided are atomic layer deposition, sputtering, and evaporation as methods of depositing desired materials for forming the above-mentioned multilayer dielectric stack.

Claims

1. An integrated circuit (IC) structure for an IC comprising a multilayer dielectric stack comprising:

a) a first dielectric layer comprising a first dielectric material overlying a semiconductor substrate, wherein the first dielectric material is selected from the group consisting of ZrO₂, and HfO₂;

b) a second dielectric layer comprising a second dielectric material overlying the first dielectric layer wherein the second dielectric material is selected from the group consisting of Al₂O₃, AlN, SiN and Si₃N₄;

c) a third dielectric layer comprising the first dielectric material overlying the first and second dielectric layers; and

d) an electrode overlying the dielectric stack.

2. The integrated circuit structure as in claim 1, wherein the first dielectric layer is less than 50 angstroms thick.

3. The integrated circuit structure as in claim 1, wherein the first dielectric layer is between approximately 2 and 5 angstroms thick.

4. The integrated circuit structure as in claim 1, wherein the second dielectric layer is less than 50 angstroms thick.

5. The integrated circuit structure as in claim 1, further comprising an oxidation barrier interposed between the first dielectric layer and the semiconductor substrate.

6. The integrated circuit structure as in claim 5, wherein the oxidation barrier is composed of material selected from the group consisting of silicon nitride and silicon oxynitride.

7. The integrated circuit structure as in claim 1, wherein a plurality of alternating layers of the first dielectric material and the second dielectric material are interposed between the semiconductor substrate and the electrode.

8. The integrated circuit structure as in claim 7, wherein the plurality of alternating layers has a combined thickness of between approximately 20 and 200 angstroms thick.

9. An integrated circuit (IC) structure for an IC comprising a multilayer dielectric stack comprising:

a) a first dielectric layer comprising a first dielectric material overlying a semiconductor substrate;

b) a second dielectric layer comprising a second dielectric material overlying the first dielectric layer, wherein the second dielectric layer is between approximately 2 and 5 angstroms thick;

c) a third dielectric layer comprising the first dielectric material overlying the first and second dielectric layers; and

d) an electrode overlying the dielectric stack.

10. The integrated circuit structure as in claim 9, wherein the first dielectric material is selected from the group consisting of ZrO₂, HfO₂, TiO₂, and Ta₂O₅, and the second dielectric material is selected from the group consisting of Al₂O₃, AlN, SiN, Si₃N₄ and SiO₂.

11. The integrated circuit structure as in claim 9, wherein the first dielectric material is selected from the group consisting of Al₂O₃, AlN, SiN, Si₃N₄ and SiO₂, and the second dielectric material is selected from the group consisting of ZrO₂, HfO₂, TiO₂, and Ta₂O₅.