Irregular grid bond pad layout arrangement for a flip chip package

• US 6,407,462 B1
• Filed: 12/30/2000
• Issued: 06/18/2002
• Est. Priority Date: 12/30/2000
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Banouvong, Nikon, Ghahghahi, Farshad
• Primary Examiner(s): Ho, Hoai V.
• Assistant Examiner(s): NGUYEN, THINH T
• Application Number:
  US09/753,000
• Time in Patent Office: 535 Days
• Field of Search: 257/787, 257/778, 257/691, 361/735, 361/760, 437/182, 437/211, 438/111
• US Class Current: 257/787
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

According to the present invention, a first plurality of solder bumps are arranged the active surface of an integrated circuit die in the form of a grid comprising a plurality of rows and a plurality of columns, where the plurality of rows are parallel to two opposing edges of the active surface and the plurality of columns are perpendicular to the plurality of rows. The plurality of columns are separated by a distance D. Each of the solder bumps in every other row is separated from an adjacent solder bump in that row by a distance 2D such that the each of these solder bumps is disposed along a first group of the plurality of columns. Each of the solder bumps in the remaining rows, is separated from an adjacent solder bump in that row by the distance 2D such that the solder bumps in the remaining rows are disposed along a second group of the plurality of columns. Each column within the second group of columns is adjacent to, and in between, two of the columns within the first group of columns. In other words, the solder bump pads are staggered.

Claims

1. A semiconductor die having an active region in a first substantially square section having four edges, the first substantially square section defining two diagonal lines, the die comprising:

a first plurality of solder bump pads on the active surface arranged in the form of a grid comprising a plurality of rows and a plurality of columns, wherein the plurality of rows are parallel to two opposing edges of the active surface and the plurality of columns are perpendicular to the plurality of rows, wherein the plurality of columns are separated by a distance D, and wherein each of a first group of solder bump pads in a first row is separated from an adjacent solder bump pad in the first row by a distance 2D such that the first group of solder bump pads is disposed along a first plurality of columns, and wherein each of a second group of solder bump pads in a second row, which is adjacent to the first row, is separated from an adjacent solder bump pad by the distance 2D such that the second group of solder bump pads is disposed along a second plurality of columns, wherein each of the second plurality of columns is adjacent to, and in between, two of the first plurality of columns; and

a plurality of core solder bumps corresponding to core power and core ground disposed within a second substantially square section centered within the first substantially square section and defined by four edges aligned substantially parallel to the four edges of the first substantially square section, the core solder bumps arranged in a grid with rows and columns separated from each other by a distance 2D.

2. The semiconductor die according to claim 1 wherein a first portion of the first plurality of solder bump pads corresponds to I/O power, a second portion of the first plurality of solder bump pads corresponds to I/O ground, and a third portion of the first plurality of solder bump pads corresponds to I/O signals.

3. The semiconductor die according to claim 1 wherein the distance between adjacent rows varies.

4. The semiconductor die according to claim 3 wherein a distance A separates adjacent rows within a first plurality of rows and a distance B separates adjacent rows within a second plurality of rows, and a single row separates the first plurality of rows from the second plurality of rows, wherein the single row is a distance A from an adjacent row within the first plurality of rows and is a distance B from an adjacent row within the second plurality of rows.

5. The semiconductor die according to claim 1 wherein the first group of solder bump pads is disposed along a first plurality of rows and wherein the second group of solder bump pads is disposed along a second plurality of rows.

6. The semiconductor die according to claim 4 wherein the first plurality of rows are between the single row and an edge of the first substantially square section, and the second plurality of rows are between the single row and an edge of the second substantially square section and wherein the distance B is greater than the distance A.

7. The semiconductor die according to claim 1 wherein the first plurality of solder bump pads are arranged in four trapezoidal regions between corresponding edges of the first and second substantially square sections.

8. The semiconductor die according to claim 1 further comprising a plurality of solder bumps disposed on the first and second groups of solder bump pads.

9. A substrate for connecting a semiconductor die to a printed circuit board, the substrate comprising:

first and second layers;

a top surface on top of the first layer with four outer edges;

a routing surface between the first and second layers;

a first plurality of via pads disposed on the top surface;

a first plurality of solder bump pads disposed on the top surface;

a first plurality of traces connecting respective ones of the first plurality of via pads with corresponding ones of the first plurality of solder bump pads;

wherein

the first plurality of via pads and the first plurality of solder bump pads are arranged in the form of a grid defined by rows that are parallel to a first one of the outer edges of the top surface and columns that are perpendicular to the rows;

the first plurality of solder bump pads arranged along a first plurality of the rows;

a first group of the first plurality of via pads is interleaved with a first group of the first plurality of solder bump pads along at least a portion of a first one of the rows.

10. The substrate according to claim 9 wherein a second group of the first plurality of via pads is interleaved with a second group of the first plurality of solder bump pads along at least a portion of a second one of the rows that is adjacent to the first one of the rows.

11. The substrate according to claim 10 further comprising:

a second plurality of solder pads disposed on the top surface, the second plurality of solder bump pads arranged on the grid, the second plurality of solder bump pads arranged along a second plurality of rows beginning with the row closest to the first one of the outer edges of the top surface;

a second plurality of traces routing the second plurality of solder bump pads;

wherein

a first one of the first plurality of signal traces is routed at least in part directly between two of the second plurality of solder bump pads that are in adjacent rows and adjacent columns.

12. The substrate according to claim 11 further comprising:

a second plurality of via pads on the routing surface, each of the second plurality of via pads directly underneath a corresponding one of the first plurality of via pads,

a first plurality of vias connecting respective ones of the first plurality of via pads with corresponding ones of the second plurality of via pads, a second plurality of vias connected to respective ones of the first plurality of via pads and extending through the routing surface,

a third plurality of traces disposed on the routing surface, wherein at least two of the third plurality of traces are routed between adjacent ones of the second plurality of vias.

13. The substrate according to claim 12 wherein three of the third plurality of traces are routed between adjacent ones of the second plurality of vias.