High speed serial-deserializer receiver

• US 6,407,682 B1
• Filed: 06/30/2000
• Issued: 06/18/2002
• Est. Priority Date: 06/30/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jones, Matthew S.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Nguyen, Khai M.
• Application Number:
  US09/609,329
• Time in Patent Office: 718 Days
• Field of Search: 341/100, 341/101, 341/141, 341/142, 341/143, 341/146, 341/95
• US Class Current: 341/100
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
• CPC Class Codes: H04L 7/04 Speed or phase control by synchronisation signals H04L7/0075 takes precedence

Abstract

A serial-deserializer converts a high speed serial data input to a lower speed parallel output. By including this circuit on a chip, connections to the chip are made more easily. A gated voltage controlled oscillator provides clock signals to sample the data input at a high rate. The output signals are thus provided at a slower rate.

Claims

1. A receiver apparatus for a serial input comprising:

an input device for receiving said serial input and transforming digital logic levels of the signal input;

a bias generator for producing a bias control signal and a gate signal;

least one gated voltage controlled oscillator connected to said bias generator and receiving said gate signal and said bias control signal where the frequency of oscillation depends on said bias signal, said oscillator producing a plurality of output clock signals;

an output driver receiving said plurality of clock signals and said transformed serial input to produce a plurality of output signals in parallel.

2. The apparatus according to claim 1, wherein an output from said input device is connected to the output driver and the bias generator.

3. The apparatus according to claim 1, wherein an output from said input device is connected to the at least one gated voltage controlled oscillator.

4. The apparatus according to claim 1, wherein the input device includes at least one differential amplifier receiving the serial input and connected to at least one buffer which produces a buffered output.

7. The apparatus according to claim 1, wherein said bias generator includes:

a phase detector receiving an output of said input device;

a charge pump connected to an output of said phase detector; and

a voltage controlled oscillator connected to an output of said charge pump and producing an output as a second input to said phase detector;

the output of said charge pump being related to said bias signal.

8. The apparatus according to claim 7, wherein said bias generator further comprises a bias shifter for receiving the output from said charge pump and producing said bias signal.

9. The apparatus according to claim 8, wherein said bias generator further comprises a gate generator connected to the output of said input device and producing a gate signal connected to said clock generator.

10. The apparatus according to claim 1, wherein said output driver includes a shift-in circuit receiving said plurality of clock signals and said transformed serial input, and a shift-out circuit for producing said output signals.

12. The apparatus according to claim 1, wherein a bit rate of said serial input is a multiple of a bit rate of said output signals with the number of said output signals being said multiple.

13. The apparatus according to claim 1, wherein said receiver apparatus is scalable.

5. A receiver apparatus for a serial input comprising:

an input device for receiving said serial input and transforming digital logic levels of the serial input;

a bias generator for producing a bias control signal;

at least one gated voltage controlled oscillator connected to said bias signal where the frequency of oscillation depends on said bias signal, said oscillator producing a plurality of output clock signals;

an output driver receiving said plurality of clock signals and said transformed serial input to produce a plurality of output signals in parallel wherein the input device is an edge detector containing at least one differential amplifier for receiving said serial input, at least one latch producing at least two outputs, with one output related to the rising of the serial input and the other output related to the falling of the serial input.

6. The apparatus according to claim 5, wherein the frequency of each output of said latch is half that of said input.

11. A receiver apparatus for a serial input comprising:

an input device for receiving said serial input and transforming digital logic levels of the serial input;

a bias generator for producing a bias control signal;

at least one gated voltage controlled oscillator connected to said bias signal where the frequency of oscillation depends on said bias signal, said oscillator producing a plurality of output clock signals;

an output driver receiving said plurality of clock signals and said transformed serial input to produce a plurality of output signals in parallel wherein said output driver includes a shift-in circuit receiving said plurality of clock signals and said transformed serial input, and a shift-out circuit for producing said output signals wherein said output driver further comprises a detection circuit for detecting a request to align the output signal and for detecting the presence of a specific signal in said serial input to which the output signal is aligned.

14. An apparatus for deserializing a serial input comprising:

an input buffer for receiving said serial input and producing a buffered serial output;

a bias generator for receiving said buffered serial output and producing a bias control signal and a gate signal;

a clock generator for receiving said bias control signal and said gate signal and producing a plurality of clock signals;

an output driver receiving said plurality of clock signals and said buffered serial output and producing a plurality of parallel output signals.

15. The apparatus according to claim 14, wherein said input buffer comprises:

at least one differential amplifier receiving said serial input and at least one buffer producing said buffered serial output.

16. The apparatus according to claim 14, wherein said bias generator comprises:

a phase detector receiving said buffered output;

a charge pump connected to an output of said phase detector;

a voltage controlled oscillator connected to an output of said charge pump and producing an output connected to a second input of said phase detector;

said charge pump having an output which is related to said bias control signal.

17. The apparatus according to claim 16, wherein said bias generator further comprises a bias shifter for receiving said output of said charge pump and producing said bias control signal.

18. The apparatus according to claim 17, wherein said bias generator further comprises a gate generator connected to said buffered serial output and producing said gate signal.

19. An apparatus for deserializing a serial input comprising:

an input buffer for receiving said serial input and producing a buffered serial output;

a bias generator for receiving said buffered serial output and producing a bias control signal and a gate signal;

a clock generator for receiving said bias control signal and said gate signal and producing a plurality of clock signals;

an output driver receiving said plurality of clock signals and said buffered serial output and producing a plurality of parallel output signals;

wherein said clock generator includes a first and a second gated voltage controlled oscillator;

a delay element;

said first gated voltage controlled oscillator receiving said gate signal and said bias control signal and producing a first clock output;

said delay element receiving said gate signal and said bias control signal to produce a delayed gate signal where the amount of delay is controlled by said bias control signal;

said second voltage controlled oscillator receiving said delayed gate signal and said bias control signal to produce a second clock output;

a first and a second clock driver connected to said first and second clock outputs, respectively, for producing for producing four clock signals at 90°

intervals.

20. An apparatus for deserializing a serial input comprising:

an input buffer for receiving said serial input and producing a buffered serial output;

a bias generator for receiving said buffered serial output and producing a bias control signal and a gate signal;

a clock generator for receiving said bias control signal and said gate signal and producing a plurality of clock signals;

an output driver receiving said plurality of clock signals and said buffered serial output and producing a plurality of parallel output signals wherein said serial input is transformed to digital logic levels in said input buffer, said clock generator generates four clock signals at 90°

intervals, said bias generator controls the frequency of said clock generator and said output driver produces a number of parallel output signals where said number is the ratio of a bit rate of said serial input to a bit rate of said output signals.

21. An apparatus for deserializing a serial input comprising:

a clocked comparator circuit for receiving said serial input;

a plurality of receiver circuits, each connected to said clocked comparator circuit and producing outputs;

each receiver circuit including a buffer connected to said clocked comparator circuit, a bias generator connected to said buffer and producing a gate signal and a bias control signal and a clock generator receiving said gate signal and said bias control signal to produce a plurality of clock signals;

an output driver receiving outputs from each of said plurality of receiver circuits and producing a plurality of output signals in parallel.

22. The apparatus according to claim 21, wherein said bias generator comprises:

a phase detector receiving said buffered output;

a charge pump connected to an output of said phase detector;

a voltage controlled oscillator connected to an output of said charge pump and producing an output connected to a second input of said phase detector;

said charge pump having an output which is related to said bias control signal.

23. An apparatus for deserializing a serial input comprising:

a clocked comparator circuit for receiving said serial input;

a plurality of receiver circuits, each connected to said clocked comparator circuit and producing outputs;

each receiver circuit including a buffer connected to said clocked comparator circuit, a bias generator connected to said buffer and producing a gate signal and a bias control signal and a clock generator receiving said gate signal and said bias control signal to produce a plurality of clock signals;

an output driver receiving outputs from each of said plurality of receiver circuits and producing a plurality of output signals in parallel wherein said clock generator includes a first and a second gated voltage controlled oscillator;

a delay element;

said first gated voltage controlled oscillator receiving said gate signal and said bias control signal and producing a clock output;

said delay element receiving said gate signal and said bias control signal to produce a delayed gate signal where the amount of delay is controlled by said bias control signal;

said second voltage controlled oscillator receiving said delayed gate signal and said bias control signal to produce a second clock output;

a first and a second clock driver connected to said first and second clock outputs, respectively, for producing four clock signals at 90°

intervals.

24. An apparatus for deserializing a serial input, comprising:

an edge detector for receiving said serial input and producing a plurality of edge signals;

a plurality of gated voltage controlled oscillators each receiving at least one of said plurality of edge signals;

a bias generator producing a bias signal which is connected to each of said plurality of gated voltage controlled oscillators; and

an output driver for receiving outputs from said plurality of gated voltage controlled oscillators and producing a plurality of output signals in parallel.

26. The apparatus according to claim 24, wherein the bias generator includes a delay circuit for receiving a reference clock signal and producing a delayed reference clock signal;

a phase detector for receiving said reference clock signal and said delayed reference clock signal and producing an output; and

a charge pump receiving said output from said phase detector and producing said bias control signal.

25. An apparatus for deserializing a serial input, comprising:

an edge detector for receiving said serial input and producing a plurality of edge signals;

a plurality of gated voltage controlled oscillators each receiving at least one of said plurality of edge signals;

a bias generator producing a bias signal which is connected to each of said plurality of gated voltage controlled oscillators; and

an output driver for receiving outputs from said plurality of gated voltage controlled oscillators and producing a plurality of output signals in parallel wherein the edge detector comprises at least one differential amplifier for receiving said serial input, at least one latch producing at least two outputs, with one output related to the rising of the serial input and the other output related to the falling of the serial input.