CMOS DAC with high impedance differential current drivers

• US 6,407,688 B1
• Filed: 04/19/2001
• Issued: 06/18/2002
• Est. Priority Date: 08/25/1999
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Greig, David Vetea
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US09/837,928
• Publication Number:
  US 20020021236A1
• Time in Patent Office: 425 Days
• Field of Search: 341/136, 341/144, 341/133, 323/315
• US Class Current: 341/136
• CPC Class Codes: H03M 1/0604 at one point, i.e. by adjusting a single reference value, e.g. bias or gain error gain setting for range control H03M1/18
• CPC Class Codes: H03M 1/0651 by selecting the quantisation value generators in a non-sequential order, e.g. symmetrical
• CPC Class Codes: H03M 1/685 the quantisation value generators of both converters being arranged in a common two-dimensional array

Abstract

High-performance, digital-to-analog conversion (DAC) suitable for use in systems implemented with low-voltage, low-power integrated circuit fabrication processes is disclosed. Encoder circuitry receives a binary number for which an analog representation is sought. Segments of the binary number are thermometer encoded and complemented to provide signals to drive analog conversion circuitry. The analog conversion circuitry includes sets of current cells, with each cell in a set contributing an equal amount to one or the other of the complementary legs of the analog output of the converter. Each current cell is a fully differential current switch with charge canceling, fed by a regulated cascode current source. The regulated cascode current source offers uncharacteristically high impedance that contributes to good circuit performance even in low-voltage, low-power implementations. Other design factors of the current cell contribute significantly to overall performance. Hierarchical gradient symmetry cancellation techniques are also employed to reduce integral non-linearity attributable to process-related surface gradients.

Claims

1. A current cell circuit for us in digital-to-analog conversion, comprising:

a regulated cascode current source including a capacitance element and a DC bias node;

a master current bias slave including a pair of bias transistors connected in a mirror configuration; and

a differential current switch coupled to the regulated cascode current source, having first and second inputs for receiving complementary input signals, first and second outputs for presenting differential output signals and a current source connection, wherein the capacitance element is configured to reduce unwanted signal feed-through at the DC bias node.

2. The current cell of claim 1 wherein the regulated cascode current source further comprises:

a first cascode transistor having its source coupled to a DC reference source; and

a second cascode transistor having its source coupled to the drain of the first cascode transistor, and its drain coupled to the current source connection of the differential current switch.

3. The current cell of claim 2 further comprising an impedance multiplier including a transistor having its gate coupled to the drain of the first cascode transistor and the source of the second cascode transistor, and its drain coupled to the gate of the second cascode transistor.

4. The current cell of claim 3 wherein the source of the feedback transistor is coupled to the DC reference source.

5. The current cell of claim 1 wherein the differential current switch further comprises:

a first switch element disposed between the current source connection and the first output; and

a second switch element disposed between the current source connection and the second output.

6. The current cell of claim 4 wherein the differential current switch further comprises:

a first switch element disposed between the current source connection and the first output; and

a second switch element disposed between the current source connection and the second output.

7. A digital-to-analog converter circuit comprising:

encoder circuitry for producing a plurality of complementary pairs of single-bit outputs;

a master current supply including a pair of bias transistors connected in a mirror configuration;

a first current summing node;

a second current summing node;

a plurality of current cells, each current cell having;

a correspondence with one of the plurality of complementary pairs of single-bit outputs;

a regulated cascode current source coupled to the master current supply including a capacitance element and a DC bias node; and

a differential current switch having a current source connection coupled to the regulated cascode current source, a first input coupled to the first single-bit output of the corresponding complementary pair, a second input coupled to the second single-bit output of the corresponding complementary pair, a first output coupled to the first current summing node, and a second output coupled to the second current summing node, wherein the capacitance element is configured to reduce unwanted signal feed-through at the DC bias node.