Deferred scanline conversion architecture

• US 6,407,736 B1
• Filed: 06/18/1999
• Issued: 06/18/2002
• Est. Priority Date: 06/18/1999
• Status: Expired due to Term

• Current Assignee: Interval Research Corporation
• Original Assignee: Interval Research Corporation
• Inventors: Regan, Matthew James Patrick
• Primary Examiner(s): Nguyen, Phu K.
• Application Number:
  US09/336,522
• Time in Patent Office: 1,096 Days
• Field of Search: 345/422, 345/419, 345/420, 345/428, 345/426, 345/423, 345/424
• US Class Current: 345/422
• CPC Class Codes: G06T 15/00 3D [Three Dimensional] image rendering
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 15/405 using Z-buffer

Abstract

The deferred scanline converter system in accordance with the present invention receives triangle data from a front end processor, identifies the triangles that are in competition for a given pixel location, and determines the winning triangle from among the competing triangles to generate the pixel for that pixel location. The system includes a triangle buffer write logic and a scan-out logic. The triangle buffer write logic initially receives triangle data, re-orients the triangle data to top, middle, and bottom vertices, and writes the triangle data to the triangle buffer in accordance with a triangle buffer writing scheme. The writing scheme uses a coverage mask to limit the number of triangles in competition for a given pixel location (i.e., if a triangle cannot be written to the triangle buffer within the confines of the coverage mask, it will be discarded). The scan-out logic performs pixel generation so that the pixel can be generated and displayed to the monitor at the time that the pixel is generated. The scan-out logic includes a triangle cache, a column of coefficient evaluators, an array of z-interpolater processors, an image composition network, and a shading/texture mapping unit. The entire scan-out logic is pipeline for fast and efficient operation.

Claims

1. A back end graphics processing system for receiving polygon data from a front end graphics processing system for processing polygon data to generate pixels for delivery to an output system comprising a plurality of pixel locations, comprising:

a triangle buffer logic for receiving polygon data from the front end graphics system, processing the polygon data and storing the polygon data, the triangle buffer logic being configured to store for each pixel location polygon data associated with no more than a bounded number of polygons competing to be displayed in said pixel location; and

a scan-out logic coupled to the triangle buffer logic for receiving polygon data stored in the triangle buffer logic and for generating pixels during scan-out of the corresponding pixels to an output system.

2. The back end graphics processing system of claim 1, wherein the polygon data is micro-polygon data, wherein the micro-polygon data is a grouping of a plurality of samples.

3. The back end graphics processing system of claim 1, wherein the polygon data is triangle data.

4. The back end graphics processing system of claim 3, wherein the triangle buffer logic further comprises:

a triangle buffer for storing triangle data in a plurality of memory locations; and

a write logic for receiving the triangle data from the front end graphics processing system and determining a targeted memory location in the triangle buffer for writing the triangle data into the targeted memory location.

5. The back end graphics processing system of claim 4, wherein the write logic further comprises:

a bounding box logic for receiving the triangle data from the front end graphics processing system and generating a bounding box that is sized to fit the triangle data, wherein the bounding box is associated with the smallest rectangle that can fit the vertices of the triangle data; and

a triangle issue logic for using a coverage mask with predetermined dimensions and issuing N triangle data if N coverage masks are needed to cover the bounding box of the triangle data.

6. The back end graphics processing system of claim 5, wherein the N coverage masks needed to cover the bounding box for the triangle data are placed adjacent each other without overlap.

7. The back end graphics processing system of claim 6, wherein each triangle data issued for each coverage mask is associated with an initial targeted memory location, wherein the initial targeted memory location is the upper left corner of each coverage mask.

8. The back end graphics processing system of claim 4 wherein the triangle data received by the write logic is designated as new triangle data and the triangle data that may already be stored in the targeted memory location in the triangle buffer is designated as old triangle data, wherein the write logic further comprises:

a z buffer for storing z depth values of a plurality of triangle data, wherein each triangle data is associated with a particular z value at each targeted memory location; and

a comparison logic for comparing the z value of the old triangle data at the targeted memory location to the z value of the new triangle at the targeted memory location, and designating the targeted memory location for the triangle data that wins the comparison.

9. The back end graphics processing system of claim 8, wherein the comparison logic writes the new triangle data into the targeted memory location if its z value is lesser than the z value of the old triangle data at the targeted memory location.

10. The back end graphics processing system of claim 4 wherein the triangle data received by the write logic is designated as new triangle data and the triangle data that may already be stored in the targeted memory location in the triangle buffer is designated as old triangle data, wherein the write logic further comprises:

a z buffer for storing z depth values of a plurality of triangle data, wherein each triangle data is associated with a particular z value at each targeted memory location; and

a comparison logic for comparing the z value of the old triangle data at the targeted memory location to the z value of the new triangle at the targeted memory location, and designating the targeted memory location for the triangle data that wins the comparison.

11. The back end graphics processing system of claim 10, wherein the comparison logic writes the new triangle data into the targeted memory location if its z value is lesser than the z value of the old triangle data at the targeted memory location.

12. The back end graphics processing system of claim 3, wherein the plurality of memory locations correspond to screen locations at the output system.

13. The back end graphics processing system of claim 3, wherein the scan-out logic further comprises:

a first processor for receiving triangle data, slope information, and z-plane information for generating a final z depth information associated with all triangles competing for coverage at a given screen location, the final z-depth information including a z-depth value associated with the screen location; and

a second processor coupled to the first processor for receiving the final z depth information associated with all triangles that are competing for the given specific screen location and resolving the competition by selecting a triangle among the competing triangles with the lowest z depth value for the given screen location.

14. The back end graphics processing system of claim 13, further comprising a shader/texture logic for receiving an index to the winning triangle from the second processor and for generating a pixel associated with the winning triangle for delivery to the output system.

15. The back end graphics processing system of claim 13, wherein the first processor further comprises:

a column of coefficient processors having a single column of a plurality of coefficient processors for receiving triangle data, slope information, and z-plane information for generating span information, initial z depth information, and dz information, where dz is the change in z depth along an x-axis of the triangle; and

an array of z-interpolator processors having a plurality of columns and a plurality of rows of z-interpolator processors for receiving the span information, initial z depth information, and dz information from the column of coefficient processors for generating final z depth information associated with all triangles competing for coverage for each screen location.

16. The back end graphics processing system of claim 15, wherein the triangle buffer logic uses a coverage mask having dimensions J rows by K columns to determine where a particular triangle will be stored, and the column of coefficient processors includes a single column of J coefficient processors, and the array of z-interpolator processors includes J rows and 2K columns of z-interpolator processors.

17. The back end graphics processing system of claim 15, wherein each coefficient processor in the column of coefficient processors compares the current screen location to the triangle boundary, and if the current screen location is outside the triangle boundary, the coefficient processor outputs the z value associated with the left edge of the triangle as the initial z depth information, and if the current location is inside the triangle boundary, the coefficient processor outputs the z value associated with that location inside the triangle as the initial z depth information.

18. The back end graphics processing system of claim 15, wherein the span information includes the left edge of the triangle at the current row and the right edge of the triangle at the current row.

19. The back end graphics processing system of claim 15, wherein each z-interpolator processor in the array of z-interpolator processors includes:

a first logic for comparing the current screen location with the span information of the triangle to determine if the current screen location is inside or outside the triangle; and

a second logic to generate the final z depth information by using a predetermined maximum z depth value if the first logic determines that the current screen location is inside the triangle, or by adding the initial z depth information to the dz information if the current screen location is inside the triangle.

20. The back end graphics processing system of claim 13, wherein the second processor includes a plurality of comparators structured together in a tree configuration and which are coupled to the first processor for receiving the final z depth information associated with the plurality of triangles competing for coverage at a given screen location, to resolve the competition among the plurality of final z-depth information associated with the competing triangles to identify the triangle with the lowest final z depth information.

21. The back end graphics processing system of claim 3, wherein the triangle buffer logic further comprises:

a first triangle buffer containing triangle data in a plurality of memory locations which were stored therein during a first time period, wherein the triangle data will be scanned out by the scan-out logic for pixel generation during a second time period; and

a second triangle buffer for storing triangle data in a plurality of memory locations during the second time period.

22. The back end graphics processing system of claim 21, wherein the first time period and the second time period each corresponds to a vertical synchronization period associated with a video graphics driver.

23. The back end graphics processing system of claim 22, wherein the vertical synchronization period corresponds to at least 60 Hz.

24. The back end graphics processing system of claim 3, wherein the triangle buffer logic further comprises:

a first triangle buffer for storing triangle data in a plurality of memory locations during a first time period;

a second triangle buffer containing triangle data in a plurality of memory locations that will be scanned out by the scan-out logic for pixel generation during the first time period; and

double buffer logic for changing the role of the first triangle buffer and the second triangle buffer after the first period so that the first triangle buffer contains triangle data to be scanned out and the second triangle buffer will be used for the storage of triangle data.

25. A triangle buffer logic in a back end graphics processor for receiving triangle data from a front end graphics processor and processing the triangle data in preparation for scan-out to an output system comprising a plurality of pixel locations, comprising:

a triangle buffer for storing triangle data in a plurality of memory locations; and

a write logic for receiving the triangle data from the front end graphics processor and determining a targeted memory location in the triangle buffer for writing the triangle data into the targeted memory location, the write logic being configured to store for each pixel location polygon data associated with no more than a bounded number of polygons competing to be displayed in said pixel location.

26. The triangle buffer logic of claim 25, wherein the plurality of memory locations correspond to screen locations at the output system.

27. The triangle buffer logic of claim 26 wherein the triangle data received by the write logic is designated as new triangle data and the triangle data that may already be stored in the targeted memory location in the triangle buffer is designated as old triangle data, wherein the write logic further comprises:

a z buffer for storing z depth values of a plurality of triangle data, wherein each triangle data is associated with a particular z value at each targeted memory location; and

a comparison logic for comparing the z value of the old triangle data at the targeted memory location to the z value of the new triangle at the targeted memory location, and designating the targeted memory location for the triangle data that wins the comparison.

28. The triangle buffer logic of claim 27, wherein the comparison logic writes the new triangle data into the targeted memory location if its z value is lesser than the z value of the old triangle data at the targeted memory location.

29. The triangle buffer logic of claim 25, wherein the triangle data includes a set of coordinates for the triangle vertices and slope equation associated with each line segment forming the sides of the triangle data.

30. The triangle buffer logic of claim 29, wherein the set of coordinates for the triangle vertices includes z-plane equation information for generating a z-plane equation.

31. The triangle buffer logic of claim 30, wherein the triangle data further includes color information.

32. The triangle buffer logic of claim 30, wherein the triangle data further includes texture information.

33. The triangle buffer logic of claim 29, wherein the triangle buffer logic re-orders the vertices of each triangle data into top, middle, and bottom vertices and stores the triangle data in this re-ordered manner in the triangle buffer.

34. The triangle buffer logic of claim 25, wherein the write logic further comprises:

a bounding box logic for receiving the triangle data from the front end graphics processor and generating a bounding box that is sized to fit the triangle data, wherein the bounding box is associated with the smallest rectangle that can fit the vertices of the triangle data; and

a triangle issue logic for using a coverage mask with predetermined dimensions and issuing N triangle data if N coverage masks are needed to cover the bounding box of the triangle data.

35. The triangle buffer logic of claim 34, wherein the N coverage masks needed to cover the bounding box for the triangle data are placed adjacent to each other without overlap.

36. The triangle buffer logic of claim 35, wherein each triangle data issued for each coverage mask is associated with an initial targeted memory location, wherein the initial targeted memory location is the upper left corner of each coverage mask.

37. The triangle buffer of claim 34 wherein the triangle data received by the write logic is designated as new triangle data and the triangle data that may already be stored in the targeted memory location in the triangle buffer is designated as old triangle data, wherein the write logic further comprises:

a z buffer for storing z depth values of a plurality of triangle data, wherein each triangle data is associated with a particular z value at each targeted memory location; and

a comparison logic for comparing the z value of the old triangle data at the targeted memory location to the z value of the new triangle at the targeted memory location, and designating the targeted memory location for the triangle data that wins the comparison.

38. The triangle buffer of claim 37, wherein the comparison logic writes the new triangle data into the targeted memory location if its z value is lesser than the z value of the old triangle data at the targeted memory location.

39. A method of writing polygon data to a triangle buffer in a graphics processing system, the polygon data associated with a polygon and the graphics processing system being associated with an output system comprising a plurality of pixel locations, comprising steps:

defining a coverage mask, the coverage mask serving to limit the storage of polygon data such that no more than a bounded number of polygons are competing to be displayed in any given pixel location;

receiving a new polygon data associated with a polygon from a front end graphics system in any order;

system in any order;

selecting an initial target memory location in the triangle buffer within the confines of the coverage mask for writing the new polygon data, where the initial target memory location can be anywhere on the triangle buffer depending on the location of the polygon on an output system; and

writing the new polygon data into the initial target memory location in the triangle buffer upon satisfaction of a set of triangle buffer write conditions.

40. The method of claim 39, wherein the polygon data is micro-polygon data, wherein the micro-polygon data is a grouping of a plurality of samples.

41. The method of claim 39, wherein the polygon data is triangle data corresponding to a triangle and the new polygon data is new triangle data.

42. The method of claim 41, wherein the initial target memory location is the memory location in the triangle buffer associated with the upper left corner of the coverage mask.

43. The method of claim 41, wherein the step of writing further comprises steps:

writing the new triangle data into the initial target memory location in the triangle buffer if no other triangle data had been previously stored in the initial target memory location; and

writing the new triangle data into the initial target memory location in the triangle buffer if its z value is lesser than the z value of an old triangle data, if the old triangle data had been previously stored at the initial target memory location.

44. The method of claim 43, wherein the step of writing further comprises steps:

determining another target memory location within the confines of the coverage mask if the new triangle data is unsuccessful in writing to a previous target memory location; and

discarding the new triangle data if it is unsuccessful in writing to any target memory location within the confines of the coverage mask.

45. The method of claim 43, wherein the step of writing further comprises steps:

displacing the old triangle data, now designated as displaced triangle data, from a target memory location if the new triangle data is associated with a z depth value that is lesser than the z depth value of the old triangle data;

re-positioning the coverage mask so that the upper left corner of the coverage mask is associated with the memory location where the displaced triangle data was previously stored but displaced from;

determining another target memory location within the confines of the re-positioned coverage mask for the displaced triangle data;

writing the displaced triangle data into the target memory location in the triangle buffer if no other triangle data had been previously stored in the target memory location; and

writing the displaced triangle data into the target memory location in the triangle buffer if its z value is lesser than the z value of an old triangle data, if the old triangle data had been previously stored at the target memory location.

46. The method of claim 41, further comprising step:

performing triangle data culling to discard those triangles whose respective surface areas are less than the surface area of a pixel.

47. The method of claim 41, further comprising step:

reordering the vertices of the triangle into top, middle, and bottom vertices; and

writing the new triangle data into the initial target memory location by writing the vertices in the format of the reordered vertices.

48. A method of writing triangle data to a triangle buffer in a graphics processing system, the triangle data associated with a triangle and the graphics processing system being associated with an output system comprising a plurality of pixel locations, comprising steps:

defining a coverage mask, the coverage mask serving to limit the storage of polygon data such that no more than a bounded number of polygons are competing to be displayed in any given pixel location;

receiving a new triangle data associated with a triangle from a front end graphics system;

defining a bounding box for the triangle;

determining the number of non-overlapping coverage masks that are needed to cover the bounding box;

issuing as many new triangle data as there are coverage masks that are needed to cover the bounding box; and

writing the new triangle data into a memory location in the triangle buffer within the confines of the coverage masks upon satisfaction of a set of triangle buffer write conditions.

49. The method of claim 48, wherein the step of writing further comprises steps:

selecting a plurality of target memory locations in the triangle buffer within the confines of the coverage mask for writing the new triangle data, where each coverage mask is associated with a target memory location; and

writing the new triangle data into the plurality of target memory locations in the triangle buffer upon satisfaction of a set of triangle buffer write conditions.

50. The method of claim 49, wherein the plurality of target memory location is initially the memory location in the triangle buffer associated with the upper left corner of each coverage mask.

51. The method of claim 50, wherein the step of writing further comprises steps:

selecting a target memory location among the plurality of target memory locations;

writing the new triangle data into a target memory location among the plurality of target memory locations in the triangle buffer if no other triangle data had been previously stored in the selected target memory location; and

writing the new triangle data into the selected target memory location in the triangle buffer if its z value is lesser than the z value of an old triangle data, if the old triangle data had been previously stored at the selected target memory location.

52. The method of claim 51, wherein the step of writing the new triangle data into the plurality of target memory locations further comprises steps:

determining another target memory location within the confines of the coverage mask if the new triangle data is unsuccessful in writing to a previously selected target memory location; and

discarding the new triangle data if it is unsuccessful in writing to any selected target memory location within the confines of its coverage mask.

53. The method of claim 51, wherein the step of, writing the new triangle data into the plurality of target memory locations further comprises steps:

displacing the old triangle data, now designated as displaced triangle data, from the selected target memory location if the new triangle data is associated with a z depth value that is lesser than the z depth value of the old triangle data;

re-positioning the coverage mask so that the upper left corner of the coverage mask is associated with the memory location where the displaced triangle data was previously stored but displaced from;

determining another target memory location within the confines of the re-positioned coverage mask for the displaced triangle data;

writing the displaced triangle data into the another target memory location in the triangle buffer if no other triangle data had been previously stored in the another target memory location; and

writing the displaced triangle data into the another target memory location in the triangle buffer if its z value is lesser than the z value of an old triangle data, if the old triangle data had been previously stored at the another target memory location.

54. A method of writing a plurality of triangle data to a triangle buffer in a graphics processing system, each triangle data associated with a triangle that is used to render an image to an output device and the graphics processing system being associated with an output system comprising a plurality of pixel locations, comprising steps:

defining a coverage mask, the coverage mask serving to limit the storage of polygon data such that no more than a bounded number of polygons are competing to be displayed in any given pixel location;

receiving a plurality of triangle data associated with a plurality of triangles from a front end graphics system;

defining a bounding box for each triangle;

determining the number of non-overlapping coverage masks that are needed to cover each bounding box;

issuing as many triangle data as there are coverage masks that are needed to cover each bounding box; and

writing each triangle data into at least one memory location in the triangle buffer, wherein a triangle data associated with a triangle is written to at most one memory location within the confines of its coverage mask upon satisfaction of a set of triangle buffer write conditions.

55. The method of claim 54, wherein the step of writing further comprises steps:

selecting a plurality of target memory locations in the triangle buffer within the confines of the coverage masks for writing the triangle data, where each coverage mask is associated with a target memory location for a triangle; and

writing the plurality of triangle data into the plurality of target memory locations in the triangle buffer upon satisfaction of a set of triangle buffer write conditions.

56. A method of generating pixels from triangle data in a graphics processing system, the triangle data associated with a triangle for rendering an image on an output device, comprising steps:

defining a coverage mask having particular dimensions;

receiving a new triangle data associated with a triangle from a front end graphics system, the triangle associated with any location on the output device;

writing the new triangle data into a memory location in the triangle buffer within the confines of the coverage mask upon satisfaction of a set of triangle buffer write conditions, the coverage mask providing a bounded set of possible memory locations for storage of the new triangle data in the triangle buffer; and

generating a pixel based on the stored triangle data in the triangle buffer using a limited set of processors that are based on the particular dimensions of the coverage mask.

57. The method of claim 56, wherein the particular dimensions of the coverage mask are J rows by K columns, and the bounded set of possible memory locations for storage of the new triangle data is J*K memory locations.

58. The method of claim 57, wherein the step of generating pixels further comprises steps:

defining a sliding mask for identifying those triangles that are in competition for coverage at each output device location for which a pixel should be generated;

moving the sliding mask across the triangle buffer for determining a current output device location; and

identifying a visible triangle among the plurality of triangles that are competing for coverage at the current output device location.

59. The method of claim 58, wherein the sliding mask has dimensions J rows by K columns.

60. The method of claim 58, wherein the sliding mask has dimensions J rows by 2*K columns.

61. The method of claim 58, further comprising step:

loading triangle data in the side of the sliding mask to the right of the current output device location.

62. The method of claim 61, wherein the step of identifying further comprises:

determining whether the current output device location is inside or outside a triangle;

identifying those triangles whose respective boundaries encompass the current output device location; and

resolving the competition among the competing triangles by selecting the triangle whose z depth value is the lowest at the current output device location.

63. The method of claim 57, wherein the step of generating pixels further comprises steps:

receiving triangle data from J adjacent rows of the triangle buffer;

identifying those triangles from the triangle data in these J adjacent rows that are in competition for coverage at a current output device location; and

resolving the competition among the competing triangles by selecting the triangle whose z depth value is the lowest at the current output device location.

64. The method of claim 57, wherein the step of generating pixels further comprises steps:

receiving triangle data, slope information, and z-plane information for generating a final z depth information associated with all triangles competing for coverage at each output device location; and

generating the final z depth information associated with all triangles that are competing for the given output device location and resolving the competition by selecting the triangle with the lowest z depth value among the competing triangles for the given output device location.

65. The method of claim 56, further comprising steps:

defining a bounding box for the triangle;

determining the number of non-overlapping coverage masks that are needed to cover the bounding box;

issuing as many new triangle data as there are coverage masks that are needed to cover the bounding box; and

writing the new triangle data into a memory location in the triangle buffer within the confines of the coverage masks upon satisfaction of a set of triangle buffer write conditions.

66. The method of claim 65, wherein the step of writing further comprises steps:

selecting a plurality of target memory locations in the triangle buffer within the confines of the coverage mask for writing the new triangle data, where each coverage mask is associated with a target memory location; and

writing the new triangle data into the plurality of target memory locations in the triangle buffer upon satisfaction of a set of triangle buffer write conditions.

67. The method of claim 66, wherein the step of writing further comprises steps:

selecting a target memory location among the plurality of target memory locations;

writing the new triangle data into a target memory location among the plurality of target memory locations in the triangle buffer if no other triangle data had been previously stored in the selected target memory location; and

writing the new triangle data into the selected target memory location in the triangle buffer if its z value is lesser than the z value of an old triangle data, if the old triangle data had been previously stored at the selected target memory location.

68. The method of claim 67, wherein the step of writing the new triangle data into the plurality of target memory locations further comprises steps:

determining another target memory location within the confines of the coverage mask if the new triangle data is unsuccessful in writing to a previously selected target memory location; and

discarding the new triangle data if it is unsuccessful in writing to any selected target memory location within the confines of its coverage mask.

69. The method of claim 67, wherein the step of writing the new triangle data into the plurality of target memory locations further comprises steps:

displacing the old triangle data, now designated as displaced triangle data, from the selected target memory location if the new triangle data is associated with a z depth value that is lesser than the z depth value of the old triangle data;

re-positioning the coverage mask so that the upper left corner of the coverage mask is associated with the memory location where the displaced triangle data was previously stored but displaced from;

determining another target memory location within the confines of the re-positioned coverage mask for the displaced triangle data;

writing the displaced triangle data into the another target memory location in the triangle buffer if no other triangle data had been previously stored in the another target memory location; and

writing the displaced triangle data into the another target memory location in the triangle buffer if its z value is lesser than the z value of an old triangle data, if the old triangle data had been previously stored at the another target memory location.

70. A scan-out logic in a back in a back end graphics processor for receiving and processing polygon data associated with each polygon in preparation for scan-out of the corresponding pixels to pixel locations at an output system, comprising:

a first processor for receiving polygon data from a buffer that stores polygon data and processing the polygon data to determine intermediate data that will be used for determining the visible polygon for each pixel location; and

a second processor coupled to the first processor for determining the visible polygon for each pixel location and for generating pixels during scan-out of the corresponding pixels to the output system, the pixels corresponding to the visible polygons at each pixel location.

71. The scan-out logic of claim 70, wherein the polygon data is micro-polygon data, wherein the micro-polygon data is a grouping of a plurality of samples.

72. The scan-out logic of claim 70, wherein the polygon data is triangle data, the polygon is a triangle.

73. The scan-out logic of claim 72, wherein the first processor further comprises:

a first logic for receiving triangle data, slope information, and z-plane information for generating a final z depth information associated with all triangles competing for coverage at each screen location.

74. The scan-out logic of claim 73, wherein the second processor further comprises:

a second logic coupled to the first processor for receiving the final z depth information associated with all triangles that are competing for the given specific screen location and resolving the competition by selecting a winning triangle among the competing triangles for the given screen location in accordance with a z depth metric.

75. The scan-out logic of claim 74, further comprising a shader/texture logic for receiving an index to the winning triangle from the second processor and for generating a pixel associated with the winning triangle for delivery to the output system.

76. The scan-out logic of claim 74, wherein the z depth metric determines the winner among the competing triangles by selecting the triangle with the lowest z depth value.

77. The scan-out logic of claim 74, wherein the first processor further comprises:

a column of coefficient processors having a single column of a plurality of coefficient processors for receiving triangle data, slope information, and z-plane information for generating span information, initial z depth information, and dz information, where dz is the change in z depth along an x-axis of the triangle; and

an array of z-interpolator processors having a plurality of columns and a plurality of rows of z-interpolator processors for receiving the span information, initial z depth information, and dz information from the column of coefficient processors for generating final z depth information associated with all triangles competing for coverage for each screen location.

78. The scan-out logic of claim 77, wherein the column of coefficient processors has J coefficient processors and the array of z-interpolator processors has K columns and J rows of z-interpolator processors.

79. The scan-out logic of claim 77, wherein each coefficient processor in the column of coefficient processors compares the current screen location to the triangle boundary, and if the current screen location is outside the triangle boundary, the coefficient processor outputs the z value associated with the left edge of the triangle as the initial z depth information, and if the current location is inside the triangle boundary, the coefficient processor outputs the z value associated with that location inside the triangle as the initial z depth information.

80. The scan-out logic of claim 77, wherein the span information includes the left edge of the triangle at the current row and the right edge of the triangle at the current row.

81. The scan-out logic of claim 77, wherein the array of z-interpolator processors is a single-instruction multiple data (SIMD) array.

82. The scan-out logic of claim 77, wherein each z-interpolator processor in the array of z-interpolator processors includes:

a first logic for comparing the current screen location with the span information of the triangle to determine if the current screen location is inside or outside the triangle; and

a second logic to generate the final z depth information by using a predetermined maximum z depth value if the first logic determines that the current screen location is inside the triangle, or by adding the initial z depth information to the dz information if the current screen location is inside the triangle.

83. The scan-out logic of claim 74, wherein the second processor includes a plurality of comparators structured together in a tree configuration and which are coupled to the first processor for receiving the final z depth information associated with the plurality of triangles competing for coverage at a given screen location, to resolve the competition among the plurality of final z-depth information associated with the competing triangles to identify the triangle with the lowest final z depth information.

84. The scan-out logic of claim 72, further comprising:

a triangle buffer for the storage of triangle data, wherein a coverage mask of dimensions J rows by K columns was used to store the triangle data associated with each triangle.

85. The scan-out logic of claim 84, wherein the first processor includes an array of processors, wherein the first processor includes at most J rows by (2*K+1) columns of processors within the array of processors for receiving triangle data to generate the intermediate data.