Memory array organization and related test method particularly well suited for integrated circuits having write-once memory arrays

• US 6,407,953 B1
• Filed: 02/02/2001
• Issued: 06/18/2002
• Est. Priority Date: 02/02/2001
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Cleeves, James M.
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US09/775,956
• Time in Patent Office: 501 Days
• Field of Search: 365/201, 365/200, 365/220, 365/185.09
• US Class Current: 365/201
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells

Abstract

In a preferred integrated circuit embodiment, a write-once memory array includes at least one test bit line which provides a respective test memory cell at the far end of each respective word line relative to its word line driver, and further includes at least one test word line which provides a respective test memory cell at the far end of each respective bit line relative to its bit line driver. An intra-layer short between word lines may be detected, such as during manufacturing testing, by biasing adjacent word lines to different voltages and detecting whether any leakage current flowing from one to another exceeds that normally accounted for by the memory cells and other known circuits. Intra-layer bit line shorts and inter-layer word line and bit line shorts may also be similarly detected. An “open” in a word line or bit line may be detected by trying to program the test memory cell at the far end of each such word line or bit line. If successfully programmed, the continuity of each word line and bit line is assured, and the programming circuitry for each word line and bit line is also known to be functional.

Claims

1. In an integrated circuit including a write-once memory array of memory cells, each respectively coupled between a respective one of a plurality of word lines and a respective one of a plurality of bit lines, a test method comprising the steps of:

providing at least one test word line and at least one test bit line for the array;

providing a first plurality of test memory cells, each respectively connected between a respective word line and an associated one of the at least one test bit line;

providing a second plurality of test memory cells, each respectively connected between a respective bit line and an associated one of the at least one test word line;

biasing predetermined ones of the first and second plurality of test memory cells, in groups of at least one test memory cell at a time, to ascertain at least one characteristic of the test memory cells; and

using the at least one ascertained characteristic of the test memory cells to predict whether related memory cells in the array will program correctly.

2. The method as recited in claim 1 wherein:

each of the first and second plurality of test memory cells is characteristically identical to the memory cells of the array.

3. The method as recited in claim 1 wherein:

each of the first and second plurality of test memory cells is characteristically similar but not identical to memory cells of the array.

4. The method as recited in claim 1 wherein:

every respective word line has a respective test memory cell connected thereto.

5. The method as recited in claim 1 wherein:

every respective bit line has a respective test memory cell connected thereto.

6. The method as recited in claim 1 wherein:

the memory array comprises a three-dimensional memory array.

7. The method as recited in claim 1 wherein:

the biasing step comprises impressing a particular voltage across a given test memory cell sufficient to program the test memory cell; and

the at least one characteristic comprises whether the given test memory cell is successfully programmed.

8. The method as recited in claim 1 wherein:

the biasing step comprises impressing a particular voltage across a given test memory cell below that sufficient to program the test memory cell; and

the at least one characteristic comprises a measured leakage current through the given test memory cell under bias.

9. The method as recited in claim 1 wherein:

the predetermined ones of the first and second plurality of test memory cells comprise all of the test memory cells.

10. The method as recited in claim 1 wherein:

the predetermined ones of the first and second plurality of test memory cells comprise some but not all of the test memory cells.

11. The method as recited in claim 1 wherein the biasing step comprises:

sequentially driving each respective word line to a first predetermined voltage while driving its associated test bit line to a second predetermined voltage to bias each respective test memory cell connected therebetween; and

sequentially driving each respective bit line to the second predetermined voltage while driving its associated test word line to the first predetermined voltage to bias each respective test memory cell connected therebetween.

12. The method as recited in claim 1 wherein:

each respective one of the first plurality of test memory cells is connected to its respective word line on an opposite side of the memory array relative to a respective programming driver for the respective word line; and

each respective one of the second plurality of test memory cells is connected to its respective bit line on an opposite side of the memory array relative to a respective programming driver for the respective bit line.

13. In an integrated circuit including a programmable memory array of programmable memory cells, each respectively coupled between a respective one of a plurality of word lines and a respective one of a plurality of bit lines, a test method comprising the steps of:

providing at least one test word line and at least one test bit line for the array;

providing a first plurality of test memory cells, each respectively connected between a respective word line and an associated one of the at least one test bit line;

providing a second plurality of test memory cells, each respectively connected between a respective bit line and an associated one of the at least one test word line;

programming each test memory cell;

predicting which memory cells in the array will correctly program based upon which test memory cells are successfully programmed during the programming step, without actually programming any memory cells.

14. The method as recited in claim 13 further comprising:

reading unprogrammed memory cells before and after programming certain test memory cells to confirm operation of memory array read circuitry.

15. The method as recited in claim 13 wherein:

the memory array is a one-time programmable array.

16. The method as recited in claim 13 wherein:

the memory array is three-dimensional array having at least two planes of memory cells.

17. The method as recited in claim 16 wherein:

the memory array is a one-time programmable array.

18. The method as recited in claim 13 wherein:

each test memory cell coupled to a test bit line is coupled to its respective word line at an end opposite a programming driver for the respective word line.

19. The method as recited in claim 13 wherein:

each test memory cell coupled to a test word line is coupled to its respective bit line at an end opposite a programming driver for the respective bit line.

20. The method as recited in claim 13 further comprising:

biasing each respective word line and bit line, in groups of at least one such line at a time, to a voltage different from that of its adjacent conductive lines;

determining whether leakage current exceeding a predetermined value is supported by a group of biased lines; and

qualifying at least one attribute of the memory array based upon the leakage current determinations.

21. The method as recited in claim 13 further comprising:

impressing a particular voltage across respective memory cells below that sufficient to program the memory cells; and

predicting whether a respective memory cell in the array will correctly program based at least in part upon the magnitude of any leakage current flowing through the respective memory cell during the impressing step.

22. The method as recited in claim 21 wherein:

the particular voltage is approximately 60-80% of an expected programming voltage for the memory cells.

23. An integrated circuit comprising:

a write-once memory array of memory cells, each respectively coupled between a respective one of a plurality of word lines and a respective one of a plurality of bit lines;

at least one test word line and at least one test bit line for the array;

a first plurality of test memory cells, each respectively connected between a respective word line and an associated one of the at least one test bit line;

a second plurality of test memory cells, each respectively connected between a respective bit line and an associated one of the at least one test word line;

terminal circuitry for biasing predetermined ones of the first and second plurality of test memory cells, in groups of at least one test memory cell at a time, and for ascertaining at least one characteristic of the test memory cells useful for predicting whether related memory cells in the array will program correctly.

24. The integrated circuit as recited in claim 23 wherein:

each of the first and second plurality of test memory cells is characteristically identical to the memory cells of the array.

25. The integrated circuit as recited in claim 23 wherein:

each of the first and second plurality of test memory cells is characteristically similar but not identical to memory cells of the array.

26. The integrated circuit as recited in claim 23 wherein:

every respective word line has a respective test memory cell connected thereto.

27. The integrated circuit as recited in claim 23 wherein:

every respective bit line has a respective test memory cell connected thereto.

28. The integrated circuit as recited in claim 23 wherein:

the memory array comprises a three-dimensional memory array.

29. The integrated circuit as recited in claim 23 wherein:

the terminal circuitry is arranged to impress a particular voltage across a given test memory cell sufficient to program the test memory cell; and

the at least one characteristic comprises whether the given test memory cell is successfully programmed.

30. The integrated circuit as recited in claim 23 wherein:

the terminal circuitry is arranged to impress a particular voltage across a given test memory cell below that sufficient to program the test memory cell; and

the at least one characteristic comprises a measured leakage current through the given test memory cell under bias.

31. The integrated circuit as recited in claim 23 wherein:

the predetermined ones of the first and second plurality of test memory cells comprise all of the test memory cells.

32. The integrated circuit as recited in claim 23 wherein:

the predetermined ones of the first and second plurality of test memory cells comprise some but not all of the test memory cells.

33. The integrated circuit as recited in claim 23 wherein:

the terminal circuitry is arranged to sequentially drive each respective word line to a first predetermined voltage and drive its associated test bit line to a second predetermined voltage, to bias each respective test memory cell connected therebetween; and

the terminal circuitry is arranged to sequentially drive each respective bit line to the second predetermined voltage and drive its associated test word line to the first predetermined voltage, to bias each respective test memory cell connected therebetween.

34. The integrated circuit as recited in claim 23 wherein:

each respective one of the first plurality of test memory cells is connected to its respective word line on an opposite side of the memory array relative to a respective programming driver for the respective word line; and

each respective one of the second plurality of test memory cells is connected to its respective bit line on an opposite side of the memory array relative to a respective programming driver for the respective bit line.