×

Semiconductor memory device of DDR configuration having improvement in glitch immunity

  • US 6,407,963 B1
  • Filed: 10/13/2000
  • Issued: 06/18/2002
  • Est. Priority Date: 10/19/1999
  • Status: Expired due to Term
First Claim
Patent Images

1. A semiconductor device comprising:

  • an internal circuit operating based on a first clock signal which supplied from a first external terminal;

    an input circuit including an input section for taking in write data based on a second clock signal and an output section connected to said input section, the second clock signal being performed level transition a prescribed number of times in response to the write data; and

    a logic circuit masking noise in the second clock signal by the logic of the first clock signal and the second clock signal and outputting a third clock signal, the noise being arisen during the final level transition of the second clock signal, wherein said input section outputs the write data based on the second clock signal, and wherein said output section outputs the write data based on the third clock signal.

View all claims
  • 9 Assignments
Timeline View
Assignment View
    ×
    ×