Semiconductor memory device of DDR configuration having improvement in glitch immunity
First Claim
1. A semiconductor device comprising:
- an internal circuit operating based on a first clock signal which supplied from a first external terminal;
an input circuit including an input section for taking in write data based on a second clock signal and an output section connected to said input section, the second clock signal being performed level transition a prescribed number of times in response to the write data; and
a logic circuit masking noise in the second clock signal by the logic of the first clock signal and the second clock signal and outputting a third clock signal, the noise being arisen during the final level transition of the second clock signal, wherein said input section outputs the write data based on the second clock signal, and wherein said output section outputs the write data based on the third clock signal.
9 Assignments
0 Petitions
Accused Products
Abstract
A semiconductor memory device of a DDR configuration improved in glitch immunity and the convenience of use is to be provided. It is a dynamic type RAM the operation of whose internal circuit is controlled in synchronism with a clock signal; an input circuit is provided in which a second clock signal inputted when in write operation is used to take in a plurality of write data serially inputted in response to that signal into a plurality of first latch circuits, and said first clock signal is used to take the write data taken into the first latch circuits into the second latch circuit to convey them to an input/output data bus; a logic circuit is provided to mask, in accordance with the logic of the first clock signal and the second clock signal, any noise arising at the end of the second clock signal, and a third clock signal is generated and supplied to the first latch circuits which output the write data to at least the input of the second latch circuits.
63 Citations
22 Claims
-
1. A semiconductor device comprising:
-
an internal circuit operating based on a first clock signal which supplied from a first external terminal;
an input circuit including an input section for taking in write data based on a second clock signal and an output section connected to said input section, the second clock signal being performed level transition a prescribed number of times in response to the write data; and
a logic circuit masking noise in the second clock signal by the logic of the first clock signal and the second clock signal and outputting a third clock signal, the noise being arisen during the final level transition of the second clock signal, wherein said input section outputs the write data based on the second clock signal, and wherein said output section outputs the write data based on the third clock signal. - View Dependent Claims (2, 3, 4, 5, 6)
a second terminal inputted the second clock, wherein said second terminal inputs an intermediate level of the second clock except in write and read operation.
-
-
3. The semiconductor device according to claim 1,
wherein said input section has a first register circuit for serially transferring the write data which is inputted in synchronism with the rising edge of the second clock signal and a second register circuit for serially transferring the write data which is inputted in synchronism with the falling edge of the second clock signal, and wherein said output section has a pair of latch circuits matching said first and second registers circuit. -
4. The semiconductor device according to claim 1,
wherein said logic circuit has a flip-flop circuit which is set at the timing of the transition of the first clock signal or of the second clock signal whichever comes earlier and is reset at the timing of the transition of either whichever comes later, and wherein said flip-flop circuit generates a pulse by the set/reset operation and outputs the pulse as said third clock signal. -
5. The semiconductor device according to claim 1,
wherein said logic circuit has a flip-flop circuit which is set at the timing of the transition of the first clock signal from one level to the other and is reset at the timing of the transition of the second clock signal from one level to the other, and wherein said flip-flop circuit generates a pulse by the set/reset operation and outputs as the pulse the third clock signal. -
6. The semiconductor device according to claim 1,
wherein said semiconductor device is a synchronous DRAM of a double data rate (DDR) configuration.
-
7. A semiconductor device comprising:
-
an internal circuit operating based on a first clock signal;
a clock generating circuit having a first input node to which the first clock signal is inputted, a second input node to which a second clock signal is inputted, and an output node which outputs a third clock signal; and
an input circuit having a third input node to which write data are inputted and a control node connected to the output node, wherein said clock generating circuit includes a logic circuit, and wherein when a first transition from a first level to a second level of the first clock signal is later than a second transition from a first level to a second level of the second clock signal with respect to the write data, the logic circuit detects the first transition and is changed the third clock signal from a third level to a fourth level. - View Dependent Claims (8, 9, 10, 11, 12)
wherein said input circuit further includes an input section connected to the third input node and an output section connected to said input section, wherein said input section outputs the write data to said output section based on the second clock signal, and wherein said output section outputs the write data to said internal circuit based on the third clock signal. -
9. The semiconductor device according to claim 8,
wherein said semiconductor device is a synchronous DRAM of a double data rate (DDR) configuration. -
10. The semiconductor device according to claim 7,
wherein when the first transition is earlier than the second transition, said logic circuit detects the second transition and is changed the third clock signal from the third level to the fourth level. -
11. The semiconductor device according to claim 10,
wherein said logic circuit detects a third transition from the second level to the first level of the second clock signal in response to the inputting of the write data and is changed the third clock signal from the fourth level to the third level. -
12. The semiconductor device according to claim 10,
wherein when a third transition from the second level to the first level of the second clock signal in response to the inputting of the write data is later than a fourth transition from the second level to the first level of the first clock signal in response to the inputting of said write data, said logic circuit detects the third transition and is changed the third clock signal from the fourth level to the third level, and wherein when the third transition is earlier than the fourth transition, said logic circuit detects the fourth transition and is changed the third clock signal from the fourth level to the third level.
-
-
13. A semiconductor device comprising:
-
an internal circuit operating based on a first clock signal;
a clock generating circuit having a first input node to which said first clock signal is inputted, a second input node to which a second clock signal is inputted, and an output node which outputs a third clock signal; and
an input circuit having a third input node to which write data are inputted and a control node connected to said output node, wherein said clock generating circuit detects a first transition of the first clock signal from a first level to a second level and is changed the third clock signal from a third level to a fourth level, and wherein said clock generating circuit detects a second transition of the second clock signal from a second level to a first level with respect to the write data and is changed the third clock signal from a fourth level to a third level. - View Dependent Claims (14, 15)
wherein said input circuit further includes an input section connected to the third input node and an output section connected to the input section, wherein said input section outputs the write data to said output section based on the second clock signal, and wherein said output section outputs said write data to said internal circuit based on the third clock signal. -
15. The semiconductor device according to claim 14,
wherein said semiconductor device is a synchronous DRAM of a double data rate (DDR) configuration.
-
-
16. A semiconductor device comprising:
-
an internal circuit operating based on a first clock signal;
a clock generating circuit having a first input node to which said first clock signal is inputted, a second input node to which a second clock signal is inputted, and an output node which outputs a third clock signal; and
an input circuit having a third input node to which write data are inputted and a control node connected to the output node, wherein said clock generating circuit has a logic circuit for comparing a first transition of the first clock signal from a first level to a second level with respect to the write data and a second transition of the second clock signal from a first level to a second level with respect to the write data, detecting the earlier of the first and second transitions, and being changed the third clock signal from a third level to a fourth level with respect to the write data. - View Dependent Claims (17, 18, 19)
wherein the logic circuit detects a third transition of the second clock signal from a second level to a first level with respect to the write data, and is changed the third clock signal from a fourth level to a third level with respect to the write data. -
18. The semiconductor device according to claim 17,
wherein said input circuit further includes an input section connected to the third input node and an output section connected to said input section; -
wherein said input section outputs the write data to said output section based on the second clock signal, and wherein said output section outputs said write data to said internal circuit based on the third clock signal.
-
-
19. The semiconductor device according to claim 18, wherein said semiconductor device is a synchronous DRAM of a double data rate (DDR) configuration.
-
-
20. A semiconductor device comprising:
-
an internal circuit operating based on a first clock signal;
a clock generating circuit having a first input node to which the first clock signal is inputted, a second input node to which a second clock signal is inputted, and an output node which outputs a third clock signal; and
an input circuit having a third input node to which write data are inputted and a control node connected to the output node, wherein said clock generating circuit has a logic circuit for generating the third clock signal, wherein said logic circuit is changed the third clock from a third level to a fourth level based on a first transition of the second clock signal from a second level to a first level within the period of the first clock signal, the period of the first clock signal being defined by the transition of the first clock signal from a first level to a second level, and wherein when there is a second transition of the second clock signal from the second level to the first level after the first transition within the period of the first clock signal, said logic circuit forbids the transition of the third clock signal from a third level to a fourth level based on the second transition. - View Dependent Claims (21, 22)
wherein said input circuit further includes an input section connected to said third input node and an output section connected to said input section; wherein said input section outputs the write data to said output section based on the second clock signal; and
wherein said output section outputs the write data to said internal circuit based on the transition of the third clock signal to the fourth level.
-
-
22. The semiconductor device according to claim 20,
wherein said semiconductor device is a synchronous DRAM of a double data rate (DDR) configuration.
Specification