Multi-tasking adapter for parallel network applications

• US 6,408,341 B1
• Filed: 02/02/2000
• Issued: 06/18/2002
• Est. Priority Date: 10/22/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Wilhelm, George William Jr., Feeney, James William, Olnowich, Howard Thomas
• Primary Examiner(s): Sheikh, Ayaz
• Assistant Examiner(s): DINH, KHANH Q
• Application Number:
  US09/496,736
• Time in Patent Office: 867 Days
• Field of Search: 709/250, 709/200, 709/212, 364/229.3, 364/229.5, 364/240, 364/240.9, 370/60, 370/80, 710/100
• US Class Current: 709/250
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes

Abstract

A communications apparatus is provided comprising a plurality of FIFO buffers, each with independent control and priority logic under software control for supporting different types of message traffic, both send and receive, such as comprise a multimedia server system. Processor software directs messages to specific, optimized FIFO buffers. Further, a system is provided including a plurality of nodes wherein a sending node specifies the communications path through the system, selecting specific FIFO buffers in each node for buffering its messages.

Claims

1. A store-and-forward adapter for interconnecting a nodal processor to a multi-stage network comprising:

a communication port for communicating messages with respect to said network;

a plurality of N addressable send FIFO buffer and N receive FIFO forming N FIFO buffer pairs for simultaneously executing a plurality of software applications on said nodal processor,

said send FIFO buffers each having independent control and priority logic under software control for storing and forwarding messages from said nodal processor to said communication port;

said receive FIFO buffers each having independent control and priority logic under software control for storing and forwarding messages from said communication port to said nodal processor;

priority logic for assigning a priority level to each said FIFO buffer;

said N FIFO buffers pairs including a first FIFO buffers pair executing highest priority transfers, a second FIFO buffers pair executing middle priority transfers, and a third FIFO buffers pair executing low priority transfers;

selection logic responsive to said priority logic for determining which send FIFO buffer is to forward a first next message to said communication port; and

routing means responsive to said priority means for determining which said receive FIFO buffer is to store a second next message received at said communication port.

2. The adapter of claim 1, wherein said send FIFO buffers and said receive FIFO buffers are implemented within an adapter memory separate from a nodal processor memory.

3. The adapter of claim 1, wherein one of said send FIFO buffers and one of said receive FIFO buffers form a FIFO buffer pair for sending and receiving messages with respect to a software application being executed on said nodal processor.

4. The adapter of claim 2, further comprising a plurality of sets of control registers programmable and readable by said nodal processor, one said set of control registers for controlling each said send and receive FIFO buffer.

5. The adapter of claim 4, wherein each said send and receive FIFO buffer is programmable by said nodal processor to a unique size and priority, and to a specific location in said adapter memory.

6. The adapter of claim 2, wherein a unique send and receive FIFO buffers pair is allocated to each of a plurality of software applications being executed on said nodal processor.

7. The adapter of claim 6, wherein a different priority level is assigned to each of a plurality of said FIFO buffers pairs.

8. The adapter of claim 6, wherein said plurality of software applications executed on said nodal processor are independent of each other and do not compete for shared resources in said adapter.

9. The adapter of claim 4, wherein said nodal processor selectively reads and writes said control registers and adapter memory selectively directly or from an addressed FIFO buffer.

10. The adapter of claim 9 wherein said adapter controls a plurality of send FIFO buffers and a plurality of receive FIFO buffers.

11. The adapter of claim 9, wherein said adapter controls three send FIFO buffers and three receive FIFO buffers.

12. The adapter of claim 11, further comprising a plurality of address bits encoded in the address used by said nodal processor to address said adapter, said address bits being encoded selectively to define:

first, a read or write operation to said adapter hardware control registers, where the specific register is defined by the remainder of the address bits;

second, a read or write operation to a first send FIFO buffer;

third, a read or write operation to a second send FIFO buffer;

fourth, a read or write operation to a third send FIFO buffer;

fifth, a read or write operation to said adapter memory directly, where the specific memory location is defined by the remainder of the address bits;

sixth, a read or write operation to a first receive FIFO buffer;

seventh, a read or write operation to a second receive FIFO buffer; and

eighth, a read or write operation to a third receive FIFO buffer.

13. A store-and-forward adapter for interconnecting a nodal processor to a multi-stage network, comprising:

communication means for communicating messages with respect to said network;

a plurality of N addressable send FIFO buffer and receive FIFO buffer pairs for simultaneously executing a plurality of software applications on said nodal processor,

said send FIFO buffers each having independent control and priority logic under software control for storing and forwarding messages from said nodal processor to said communication means;

said receive FIFO buffers each having independent control and priority logic under software control for storing and forwarding messages from said communication means to said nodal processor;

said N FIFO buffers pairs including a first FIFO buffer pair executing highest priority transfers, a second FIFO buffer pair executing middle priority transfers, and a third FIFO buffer pair executing low priority transfers;

selection means for determining which send FIFO buffer is to forward a first next message to said communication means; and

routing means for determining which said receive FIFO buffer is to store a second next message received at said communication means.

14. The adapter of claim 13, wherein a unique send and receive FIFO buffers pair is allocated to each of a plurality of software applications being executed on said nodal processor.

15. The adapter of claim 14, wherein a different priority level is assigned to each of a plurality of said FIFO buffers pairs.

16. The adapter of claim 13, wherein said plurality of software applications executed on said nodal processor are independent of each other and do not compete for shared resources in said adapter.

17. Method for interconnecting a nodal processor to a multi-stage network via a communication including a plurality of send FIFO buffer and receive FIFO buffer pairs for simultaneously executing a plurality of software applications, said method comprising:

operating said plurality of N addressable send FIFO buffer and receive FIFO buffer pairs, each buffer under independent software control, said send FIFO buffers for storing and forwarding messages from said nodal processor to said communication means, and said receive FIFO buffers for storing and forwarding messages from said network to said nodal processor;

assigning a priority level to each said FIFO buffer with said N FIFO buffers pairs including a first FIFO buffers pair executing highest priority transfers, a second FIFO buffers pair executing middle priority transfers, and a third FIFO buffers pair executing low priority transfers;

responsive to said priority level, determining which send FIFO buffer is to forward a first next message to network; and

responsive to said priority level, determining which said receive FIFO buffer is to store a second next message received from said network.

18. The method of claim 17, comprising the further step of allocating a unique send and receive FIFO buffers pair to each of a plurality of software applications being executed on said nodal processor.

22. The method of claim 18, wherein the priority assigned to each said sending list is different for each sending list, comprising the further steps of:

executing the highest priority list continually, one DMA Channel Program after another, until said list is empty, and thereafter executing the next highest priority list continually until it is empty or until the higher priority list becomes not empty.

23. The method claim 17, comprising the further steps of

assigning equal priority to a plurality of said sending lists;

and

executing said sending lists having equal priority in round robin order, where one DMA Channel Program is executed from each of said sending lists having the same priority before a second DMA Channel Program is executed from any of the lists having the same priority.

24. The method of claim 23, said executing step including servicing sending lists having service requests and skipping sending lists not having service requests.

19. Method for interconnecting a nodal processor to a network by way of a communication port comprising a plurality of send FIFO buffers and a plurality of receive FIFO buffers organized in a plurality of buffer pairs for simultaneously executing a plurality of software applications on said nodal processor, comprising the steps of:

storing a plurality of DMA control programs in respective DMA channels in said plurality of receive FIFO buffers in adapter memory;

responsive to a received message from said network, selecting one of said receive FIFO buffers and activating a DMA control program in one of said DMA channels;

storing said received message to nodal processor memory;

notifying said nodal processor that said DMA channel has stored said received message to nodal processor memory by posting a completion status to a status register;

reading to said nodal processor a group of status bits from said status register; and

resetting individual status bits in said status register by writing from said nodal processor.

20. The method of claim 19, comprising the further step of selectively disabling further processing by said DMA channel until said nodal processor enables said DMA channel by writing to adapter memory.

21. The method of claim 19, comprising the further step of scattering said received message to a plurality of nodal processor addresses as defined by a plurality of linked DMA programs.

25. A store-and-forward adapter for interconnecting a nodal processor as a node to a network comprising:

communication means for communicating messages with respect to said network, wherein a sending node transmits a message across the network to a receiving node;

a plurality of addressable send FIFO buffers and a plurality of addressable receive FIFO buffers forming a plurality of send and receive FIFO buffer pairs for simultaneously executing a plurality of software applications on said nodal processor;

said plurality of addressable send FIFO buffers for storing and forwarding messages from said nodal processor to said communication means;

said plurality of addressable receive FIFO buffers for storing and forwarding messages from said communication means to said nodal processor;

priority means for assigning a priority level to each said FIFO buffer with said N FIFO buffers pairs including a first FIFO buffers pair executing highest priority transfers, a second FIFO buffers pair executing middle priority transfers, and a third FIFO buffers pair executing low priority transfers;

first selection means responsive to said priority means for determining which send FIFO buffer is to forward a first next message to said communication means and second selection means for determining which one of said plurality of send FIFO buffers is to store and forward each said message, wherein the nodal processor at the sending node controls both said first and second selection means; and

routing means responsive to said priority means for determining which said receive FIFO buffer is to store a second next message received at said communication means.

26. A store-and-forward adapter for interconnecting a nodal processor as a node to a network, comprising:

communication means for communicating messages with respect to said network wherein a sending node transmits a message across the network to a receiving node;

a plurality of N send FIFO buffers and receive FIFO buffers for simultaneously executing a plurality of software applications on said nodal processor, said N FIFO buffers pairs including a first FIFO buffers pair executing highest priority transfers, a second FIFO buffers pair executing middle priority transfers, and a third FIFO buffers pair executing low priority transfers;

said plurality of addressable send FIFO buffers for storing and forwarding messages from said nodal processor to said communication means;

said plurality of addressable receive FIFO buffers for storing and forwarding messages from said communication means to said nodal processor;

first selection means for determining which send FIFO buffer is to forward a first next message to said communication means and second selection means for determining which one of said plurality of send FIFO buffers is to store and forward each message, wherein the nodal processor at the sending node controls both said first and second selection means; and

routing means for determining which said receive FIFO buffer is to store a second next message received at said communication means.

27. Method for interconnecting a nodal processor as a node to a network wherein a sending node transmits a message across the network to a receiving node via a communication port including a plurality of N addressable send FIFO buffer and receive FIFO buffer pairs for simultaneously executing a plurality of software applications, said method comprising:

operating said plurality of addressable send FIFO buffers for storing and forwarding messages from said nodal processor to said network;

operating said plurality of addressable receive FIFO buffers for storing and forwarding messages from said network to said nodal processor;

assigning a priority level to each said FIFO buffer, with said N FIFO buffers pairs including a first FIFO buffers pair executing highest priority transfers, a second FIFO buffers pair executing middle priority transfers, and a third FIFO buffers pair executing low priority transfers;

using a FIFO buffer selection means;

responsive to said priority level, determining which send FIFO buffer is to forward a first next message to network and responsive to said selection means for determining which one of said plurality of send FIFO buffers is to store and forward each message, wherein the nodal processor at the sending node controls both said priority level and said selection means and which said receive FIFO buffer is to store a second message received from said network.