Multi-tasking adapter for parallel network applications
First Claim
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1. A store-and-forward adapter for interconnecting a nodal processor to a multi-stage network comprising:
- a communication port for communicating messages with respect to said network;
a plurality of N addressable send FIFO buffer and N receive FIFO forming N FIFO buffer pairs for simultaneously executing a plurality of software applications on said nodal processor, said send FIFO buffers each having independent control and priority logic under software control for storing and forwarding messages from said nodal processor to said communication port;
said receive FIFO buffers each having independent control and priority logic under software control for storing and forwarding messages from said communication port to said nodal processor;
priority logic for assigning a priority level to each said FIFO buffer;
said N FIFO buffers pairs including a first FIFO buffers pair executing highest priority transfers, a second FIFO buffers pair executing middle priority transfers, and a third FIFO buffers pair executing low priority transfers;
selection logic responsive to said priority logic for determining which send FIFO buffer is to forward a first next message to said communication port; and
routing means responsive to said priority means for determining which said receive FIFO buffer is to store a second next message received at said communication port.
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Abstract
A communications apparatus is provided comprising a plurality of FIFO buffers, each with independent control and priority logic under software control for supporting different types of message traffic, both send and receive, such as comprise a multimedia server system. Processor software directs messages to specific, optimized FIFO buffers. Further, a system is provided including a plurality of nodes wherein a sending node specifies the communications path through the system, selecting specific FIFO buffers in each node for buffering its messages.
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Citations
27 Claims
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1. A store-and-forward adapter for interconnecting a nodal processor to a multi-stage network comprising:
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a communication port for communicating messages with respect to said network;
a plurality of N addressable send FIFO buffer and N receive FIFO forming N FIFO buffer pairs for simultaneously executing a plurality of software applications on said nodal processor, said send FIFO buffers each having independent control and priority logic under software control for storing and forwarding messages from said nodal processor to said communication port;
said receive FIFO buffers each having independent control and priority logic under software control for storing and forwarding messages from said communication port to said nodal processor;
priority logic for assigning a priority level to each said FIFO buffer;
said N FIFO buffers pairs including a first FIFO buffers pair executing highest priority transfers, a second FIFO buffers pair executing middle priority transfers, and a third FIFO buffers pair executing low priority transfers;
selection logic responsive to said priority logic for determining which send FIFO buffer is to forward a first next message to said communication port; and
routing means responsive to said priority means for determining which said receive FIFO buffer is to store a second next message received at said communication port. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
first, a read or write operation to said adapter hardware control registers, where the specific register is defined by the remainder of the address bits;
second, a read or write operation to a first send FIFO buffer;
third, a read or write operation to a second send FIFO buffer;
fourth, a read or write operation to a third send FIFO buffer;
fifth, a read or write operation to said adapter memory directly, where the specific memory location is defined by the remainder of the address bits;
sixth, a read or write operation to a first receive FIFO buffer;
seventh, a read or write operation to a second receive FIFO buffer; and
eighth, a read or write operation to a third receive FIFO buffer.
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13. A store-and-forward adapter for interconnecting a nodal processor to a multi-stage network, comprising:
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communication means for communicating messages with respect to said network;
a plurality of N addressable send FIFO buffer and receive FIFO buffer pairs for simultaneously executing a plurality of software applications on said nodal processor, said send FIFO buffers each having independent control and priority logic under software control for storing and forwarding messages from said nodal processor to said communication means;
said receive FIFO buffers each having independent control and priority logic under software control for storing and forwarding messages from said communication means to said nodal processor;
said N FIFO buffers pairs including a first FIFO buffer pair executing highest priority transfers, a second FIFO buffer pair executing middle priority transfers, and a third FIFO buffer pair executing low priority transfers;
selection means for determining which send FIFO buffer is to forward a first next message to said communication means; and
routing means for determining which said receive FIFO buffer is to store a second next message received at said communication means. - View Dependent Claims (14, 15, 16)
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17. Method for interconnecting a nodal processor to a multi-stage network via a communication including a plurality of send FIFO buffer and receive FIFO buffer pairs for simultaneously executing a plurality of software applications, said method comprising:
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operating said plurality of N addressable send FIFO buffer and receive FIFO buffer pairs, each buffer under independent software control, said send FIFO buffers for storing and forwarding messages from said nodal processor to said communication means, and said receive FIFO buffers for storing and forwarding messages from said network to said nodal processor;
assigning a priority level to each said FIFO buffer with said N FIFO buffers pairs including a first FIFO buffers pair executing highest priority transfers, a second FIFO buffers pair executing middle priority transfers, and a third FIFO buffers pair executing low priority transfers;
responsive to said priority level, determining which send FIFO buffer is to forward a first next message to network; and
responsive to said priority level, determining which said receive FIFO buffer is to store a second next message received from said network. - View Dependent Claims (18, 22, 23, 24)
executing the highest priority list continually, one DMA Channel Program after another, until said list is empty, and thereafter executing the next highest priority list continually until it is empty or until the higher priority list becomes not empty.
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23. The method claim 17, comprising the further steps of
assigning equal priority to a plurality of said sending lists; - and
executing said sending lists having equal priority in round robin order, where one DMA Channel Program is executed from each of said sending lists having the same priority before a second DMA Channel Program is executed from any of the lists having the same priority.
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24. The method of claim 23, said executing step including servicing sending lists having service requests and skipping sending lists not having service requests.
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19. Method for interconnecting a nodal processor to a network by way of a communication port comprising a plurality of send FIFO buffers and a plurality of receive FIFO buffers organized in a plurality of buffer pairs for simultaneously executing a plurality of software applications on said nodal processor, comprising the steps of:
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storing a plurality of DMA control programs in respective DMA channels in said plurality of receive FIFO buffers in adapter memory;
responsive to a received message from said network, selecting one of said receive FIFO buffers and activating a DMA control program in one of said DMA channels;
storing said received message to nodal processor memory;
notifying said nodal processor that said DMA channel has stored said received message to nodal processor memory by posting a completion status to a status register;
reading to said nodal processor a group of status bits from said status register; and
resetting individual status bits in said status register by writing from said nodal processor. - View Dependent Claims (20, 21)
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25. A store-and-forward adapter for interconnecting a nodal processor as a node to a network comprising:
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communication means for communicating messages with respect to said network, wherein a sending node transmits a message across the network to a receiving node;
a plurality of addressable send FIFO buffers and a plurality of addressable receive FIFO buffers forming a plurality of send and receive FIFO buffer pairs for simultaneously executing a plurality of software applications on said nodal processor;
said plurality of addressable send FIFO buffers for storing and forwarding messages from said nodal processor to said communication means;
said plurality of addressable receive FIFO buffers for storing and forwarding messages from said communication means to said nodal processor;
priority means for assigning a priority level to each said FIFO buffer with said N FIFO buffers pairs including a first FIFO buffers pair executing highest priority transfers, a second FIFO buffers pair executing middle priority transfers, and a third FIFO buffers pair executing low priority transfers;
first selection means responsive to said priority means for determining which send FIFO buffer is to forward a first next message to said communication means and second selection means for determining which one of said plurality of send FIFO buffers is to store and forward each said message, wherein the nodal processor at the sending node controls both said first and second selection means; and
routing means responsive to said priority means for determining which said receive FIFO buffer is to store a second next message received at said communication means.
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26. A store-and-forward adapter for interconnecting a nodal processor as a node to a network, comprising:
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communication means for communicating messages with respect to said network wherein a sending node transmits a message across the network to a receiving node;
a plurality of N send FIFO buffers and receive FIFO buffers for simultaneously executing a plurality of software applications on said nodal processor, said N FIFO buffers pairs including a first FIFO buffers pair executing highest priority transfers, a second FIFO buffers pair executing middle priority transfers, and a third FIFO buffers pair executing low priority transfers;
said plurality of addressable send FIFO buffers for storing and forwarding messages from said nodal processor to said communication means;
said plurality of addressable receive FIFO buffers for storing and forwarding messages from said communication means to said nodal processor;
first selection means for determining which send FIFO buffer is to forward a first next message to said communication means and second selection means for determining which one of said plurality of send FIFO buffers is to store and forward each message, wherein the nodal processor at the sending node controls both said first and second selection means; and
routing means for determining which said receive FIFO buffer is to store a second next message received at said communication means.
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27. Method for interconnecting a nodal processor as a node to a network wherein a sending node transmits a message across the network to a receiving node via a communication port including a plurality of N addressable send FIFO buffer and receive FIFO buffer pairs for simultaneously executing a plurality of software applications, said method comprising:
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operating said plurality of addressable send FIFO buffers for storing and forwarding messages from said nodal processor to said network;
operating said plurality of addressable receive FIFO buffers for storing and forwarding messages from said network to said nodal processor;
assigning a priority level to each said FIFO buffer, with said N FIFO buffers pairs including a first FIFO buffers pair executing highest priority transfers, a second FIFO buffers pair executing middle priority transfers, and a third FIFO buffers pair executing low priority transfers;
using a FIFO buffer selection means;
responsive to said priority level, determining which send FIFO buffer is to forward a first next message to network and responsive to said selection means for determining which one of said plurality of send FIFO buffers is to store and forward each message, wherein the nodal processor at the sending node controls both said priority level and said selection means and which said receive FIFO buffer is to store a second message received from said network.
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Specification