Semiconductor package using terminals formed on a conductive layer of a circuit board

• US 6,410,355 B1
• Filed: 01/19/2000
• Issued: 06/25/2002
• Est. Priority Date: 06/11/1998
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Wallace, Robert F.
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Geyer, Scott B.
• Application Number:
  US09/487,106
• Time in Patent Office: 888 Days
• Field of Search: 438/1-800, 257/1-930
• US Class Current: 438/15
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 23/24 solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/5388 for flat cards, e.g. credit cards cards per se G06K19/00
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1433 Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H05K 1/0268 for electrical inspection or testing
• CPC Class Codes: H05K 1/117 Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
• CPC Class Codes: H05K 2201/09127 PCB or component having an integral separable or breakable part
• CPC Class Codes: H05K 2201/10689 Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
• CPC Class Codes: H05K 2201/2018 : Presence of a frame in a printed circuit or printed circuit assembly
• CPC Class Codes: H05K 3/0052 : Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
• CPC Class Codes: H05K 3/284 : for encapsulating mounted components H05K1/185 takes precedence

Abstract

A small package is provided for a flash EEPROM memory. The small package uses terminals which are part of a bottom conductive layer of a circuit board. In this manner, the final package can be quite thin. The circuit board can be connected to the integrated circuits and passive devices and can be encapsulated in plastic or glued to a plastic cover. In this manner, a thin and relatively inexpensive package can be formed. Additionally, the circuit board can have testing connections which can be removed before forming the final package.

Claims

1. A method of making a memory card comprising:

attaching a set of circuit elements to a circuit board, the set of circuit elements including at least one integrated circuit and passive components, the circuit board having test connections and terminals on one end of the circuit board, the test connections being connected to test the set of circuit elements;

testing the set of circuit elements using the test connections;

thereafter, severing the end of the circuit board having the test connections and terminals; and

thereafter, packaging the circuit board.

2. The method of claim 1, wherein the terminals are positioned on a face of the circuit board.

3. The method of claim 2, wherein the package is such that the face of the circuit board having the terminals is exposed.

4. The method of claim 1, wherein the testing includes a burn-in testing.

5. The method of claim 1, further comprising mapping out bad memory cells using the test connections.

6. A method of making a memory card comprising:

forming contacts on a first face of a circuit board wherein the contacts are the only circuit element on the first face;

attaching a set of circuit elements comprising at least one integrated circuit including flash memory, circuit traces, and passive components to a second face of the circuit board;

forming vias through the circuit board wherein the vias connect the set of circuit elements on the second face to the contacts on the first face;

forming a one piece cover over the second face and edges of the circuit board, such that the first face of the circuit board is exposed to form substantially all of a face of the memory card.

7. The method of claim 6 wherein the step of forming the one piece cover comprises encapsulation.

8. The method of claim 6 wherein the step of forming the cover comprises attaching a plastic one piece cover.

10. The method of claim 6 further comprising encapsulating the at least one integrated circuit prior to forming the cover.

11. The method of claim 10 wherein the encapsulating of the at least one integrated circuit is performed at a lower temperature than when forming the cover, thereby protecting the at least one integrated circuit from subsequent high temperature molding.

12. The method of claim 10 wherein the passive components are not encapsulated prior to forming the cover.

13. The method of claim 10, wherein the encapsulation includes placing plastic into a mold containing the circuit board.

14. The method of claim 10, wherein the encapsulation includes clamping over terminals.

15. The method of claim 10, wherein the encapsulation includes putting plastic into a mold with multiple chambers, each chamber having a different circuit board.

16. The method of claim 6, wherein the passive components are capacitors used to covert the supplied voltage to the larger voltage required to modify the flash memory.

9. A method of making a memory card comprising:

forming a first conductive layer on a first face of a circuit board;

removing the first conductive layer except for a row of terminals spaced away from the edge of the circuit board;

forming a second conductive layer on a second face of a circuit board;

removing the second layer except for a set of circuit traces and a group of testing leads located at a first end of the circuit board;

connecting the circuit traces on the second face of the circuit board by vias to the row of terminals on the first face of the circuit board;

attaching a set of circuit elements to the circuit traces on the second face of the board;

testing the board; and

thereafter

removing the first end of the board with the group of testing leads; and

thereafter

covering the second face of the circuit board.

17. A method of making a memory card comprising:

forming a first conductive layer on a first face of a circuit board;

removing the first conductive layer except for a plurality of terminals spaced away from the edge of the circuit board;

forming a second conductive layer on a second face of a circuit board;

removing the second layer except for a set of circuit traces and a group of testing leads located at a first portion of the circuit board;

connecting the circuit traces on the second face of the circuit board by vias to the row of terminals on the first face of the circuit board;

attaching a set of circuit elements comprising at least one integrated circuit including flash memory, circuit traces, and passive components to a second face of the circuit board;

encapsulating the integrated circuit;

testing the memory card by connecting with the testing leads at the first portion of the circuit board; and

thereafter

removing the first portion of the board with the group of testing leads; and

thereafter

covering the second face of the circuit board.

18. The method of claim 17, wherein testing the board comprises mapping the memory cells of the integrated circuit.

19. The method of claim 17, wherein testing the memory card comprises mapping out defective memory cells.

20. The method of claim 17 wherein when encapsulating the integrated circuit the passive components are not encapsulated.

21. The method of claim 17, wherein connecting to the test leads is done via a removable connector.

22. The method of claim 17 wherein covering the second face further comprises covering the edges of the circuit board.

23. The method of claim 17 wherein covering the second face comprises attaching a plastic one piece cover.

24. The method of claim 17 wherein covering the second face comprises encapsulating the second face of the circuit board.

25. The method of claim 24 wherein the encapsulation is within a border frame.

26. The method of claim 17 wherein the act of covering the second face further comprises covering the edges of the circuit board.