Method for fabricating a semiconductor device

• US 6,410,414 B1
• Filed: 10/12/1999
• Issued: 06/25/2002
• Est. Priority Date: 12/28/1998
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Lee, Joo-hern
• Primary Examiner(s): Picardat, Kevin M.
• Assistant Examiner(s): COLLINS, DEVEN M
• Application Number:
  US09/416,403
• Publication Number:
  US 20020076913A1
• Time in Patent Office: 987 Days
• Field of Search: 438/612, 438/113, 438/462, 438/613, 438/614, 438/623
• US Class Current: 438/612
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0236 Shape of the insulating layers therebetween
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/1148 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/293 Organic, e.g. plastic
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01084 : Polonium [Po]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A method for fabricating a semiconductor device reduces soft errors, thereby enhancing reliability of the semiconductor device. In the method, a benzo cyclo butene (BCB) layer having a low water intake rate and an excellent blocking effect against alpha particles is formed between an alpha particle source such as a solder ball and sensitive integrated circuit devices such as a memory cell.

Claims

1. A method for fabricating a semiconductor device, comprising:

(a) forming a top metal layer including a bondpad on an integrated circuit including a memory cell;

(b) forming a passivation layer on the top metal layer, for preventing penetration of moisture or impurities;

(c) pattering the passivation layer to expose the bondpad;

(d) forming a metal pattern on the passivation layer connected to the bondpad for bondpad redistribution; and

(e) forming a plurality of insulating layers including a benzo cyclo butene (BCB) layer and a polymer layer on the metal pattern.

2. The method of claim 1, wherein forming the plurality of insulating layers comprises:

forming the BCB layer on the metal pattern; and

forming a polyimide layer on the BCB layer.

3. The method of claim 1, wherein forming the plurality of insulating layers comprises:

forming a polyimide layer on the metal pattern; and

forming the BCB layer on the polyimide layer.

4. The method of claim 1, wherein the passivation layer comprises at least one layer selected from a group consisting of a silicon nitride (SiN) layer, a titanium nitride (TiN) layer, a plasma enhanced oxide (PEOX) layer and a phosphor-silicate glass (PSG) layer.

5. The method of claim 1, wherein the BCB layer has a thickness between 10 μ

m and 100 μ

m.

6. The method of claim 1, further comprising connecting an external connecting means to the metal pattern after forming the insulating layer.

7. A method for fabricating a semiconductor device, comprising:

(a) forming a top metal layer including a bondpad on an integrated circuit including a memory cell;

(b) forming a passivation layer on the top metal layer, for preventing penetration of moisture or impurities;

(c) forming a first insulating layer on the passivation layer;

(d) patterning the first insulating layer to expose the bondpad;

(e) forming a metal pattern on the first insulating layer connected to the bondpad for bondpad redistribution; and

(f) forming a second insulating layer including a benzo cyclo butene (BCB) layer on the metal pattern for bondpad redistribution.

8. The method of claim 7, further comprising patterning the passivation layer to expose the bondpad after the step (b).

9. The method of claim 7, wherein the passivation layer comprises at least one layer selected from a group consisting of a silicon nitride (SiN) layer, a titanium nitride (TiN) layer, a plasma enhanced oxide (PEOX) layer and a phosphor-silicate glass (PSG) layer.

10. The method of claim 7, wherein the BCB layer has a thickness between 10 μ

m and 100 μ

m.

11. The method of claim 7, further comprising connecting an external connecting means to the metal pattern after the step (f).

12. The method of claim 7, wherein the first insulating layer comprises a polyimide layer.

13. A method for fabricating a semiconductor device, comprising:

(a) forming a top metal layer including a bondpad on an integrated circuit including a memory cell;

(b) forming a passivation layer on the top metal layer, for preventing penetration of moisture or impurities;

(c) forming a first insulating layer including a benzo cyclo butene (BCB) layer on the passivation layer;

(d) patterning the first insulating layer to expose the bondpad;

(e) forming a metal pattern on the first insulating layer connected to the bondpad for bondpad redistribution; and

(f) forming a second insulating layer on the metal pattern.

14. The method of claim 13, further comprising patterning the passivation layer to expose the bondpad after the step (b).

15. The method of claim 13, wherein the passivation layer comprises at least one layer selected from a group consisting of a silicon nitride (SiN) layer, a titanium nitride (TiN) layer, a plasma enhanced oxide (PEOX) layer and a phosphor-silicate glass (PSG) layer.

16. The method of claim 13, wherein the BCB layer has a thickness between 10 μ

m and 100 μ

m.

17. The method of claim 13, further comprising connecting an external connecting means to the metal pattern after the step (f).

18. The method of claim 13, wherein the second insulating layer comprises a polyimide layer.

19. A method for fabricating semiconductor device comprising:

(a) forming a top metal layer on a semiconductor substrate on which an integrated circuit is formed;

(b) forming a passivation layer on the top metal layer, the passivation layer multiple layers one of which is a benzo cyclo butene layer;

(c) patterning the passivation layer to expose the bondpad;

(d) forming a metal pattern for bondpad redistribution connected to the bondpad; and

(e) forming an insulating layer on the metal pattern.

20. The method of claim 19, further comprising connecting an external connecting means to the metal pattern after the step (e).

21. The method of claim 19, wherein the BCB layer has a thickness between 10 μ

m and 100 μ

m.

22. The method of claim 19, wherein forming the passivation layer comprises:

forming a first layer of silicon nitride (SiN) or titanium nitride (TiN);

forming a second layer of BCB; and

forming a third layer of phosphor-silicate glass (PSG) or plasma enhanced oxide (PEOX).

23. The method of claim 22, wherein the second layer is between the first and third layers.

24. The method of claim 19, wherein the insulating layer is formed of polyimide.