Damascene cap layer process for integrated circuit interconnects
First Claim
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1. A method for forming interconnects, comprising:
- providing a silicon substrate containing one or more electronic devices;
forming a first dielectric layer over said silicon substrate;
forming a second dielectric layer over said first dielectric layer wherein the dielectric constant of the second dielectric layer is less than 3.0;
forming a capping layer on said second dielectric layer wherein said capping layer consists of a material selected form the group consisting of titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium nitride (TiN), aluminum nitride (AlN), tantalum aluminide (TaAl), and tantalum aluminum nitride (TaAlN);
forming a trench in said second dielectric; and
filling said trench with a conducting material.
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Abstract
The invention describes a method for forming integrated circuit interconnects. A capping layer (50) is formed on a low k dielectric layer (40). The capping layer (50) and the low k dielectric layer (40) are etched to form a via and/or trench in the low k dielectric (4) which is filled with a conducting material (90) (95).
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Citations
6 Claims
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1. A method for forming interconnects, comprising:
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providing a silicon substrate containing one or more electronic devices;
forming a first dielectric layer over said silicon substrate;
forming a second dielectric layer over said first dielectric layer wherein the dielectric constant of the second dielectric layer is less than 3.0;
forming a capping layer on said second dielectric layer wherein said capping layer consists of a material selected form the group consisting of titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium nitride (TiN), aluminum nitride (AlN), tantalum aluminide (TaAl), and tantalum aluminum nitride (TaAlN);
forming a trench in said second dielectric; and
filling said trench with a conducting material. - View Dependent Claims (2, 3)
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4. A method for forming integrated circuit interconnects, comprising:
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providing a silicon substrate containing one or more electronic devices;
forming a first dielectric layer over said silicon substrate;
forming a second dielectric layer over said etch stop layer wherein the dielectric constant of the second dielectric layer is less than 3.0;
forming a capping layer on said second dielectric layer wherein said capping layer consists of a material selected form the group consisting of titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium nitride (TiN), aluminum nitride (AlN), tantalum aluminide (TaAl), and tantalum aluminum nitride (TaAlN);
forming a first trench in said second dielectric wherein said first trench has a first width;
forming a second trench in said second dielectric wherein said second trench has a second width different from said first width and said second trench is positioned over said first trench; and
filling said first and second trench with a conducting material. - View Dependent Claims (5, 6)
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Specification