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Damascene cap layer process for integrated circuit interconnects

  • US 6,410,426 B1
  • Filed: 07/09/2001
  • Issued: 06/25/2002
  • Est. Priority Date: 07/09/2001
  • Status: Active Grant
First Claim
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1. A method for forming interconnects, comprising:

  • providing a silicon substrate containing one or more electronic devices;

    forming a first dielectric layer over said silicon substrate;

    forming a second dielectric layer over said first dielectric layer wherein the dielectric constant of the second dielectric layer is less than 3.0;

    forming a capping layer on said second dielectric layer wherein said capping layer consists of a material selected form the group consisting of titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium nitride (TiN), aluminum nitride (AlN), tantalum aluminide (TaAl), and tantalum aluminum nitride (TaAlN);

    forming a trench in said second dielectric; and

    filling said trench with a conducting material.

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