Damascene cap layer process for integrated circuit interconnects

• US 6,410,426 B1
• Filed: 07/09/2001
• Issued: 06/25/2002
• Est. Priority Date: 07/09/2001
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Jiang, Ping, Xing, Guoqiang
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US09/901,392
• Time in Patent Office: 351 Days
• Field of Search: 438/597, 438/638, 438/618, 438/634, 438/687, 438/970, 438/689, 438/780
• US Class Current: 438/638
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: Y10S 438/97 Specified etch stop material

Abstract

The invention describes a method for forming integrated circuit interconnects. A capping layer (50) is formed on a low k dielectric layer (40). The capping layer (50) and the low k dielectric layer (40) are etched to form a via and/or trench in the low k dielectric (4) which is filled with a conducting material (90) (95).

Claims

1. A method for forming interconnects, comprising:

providing a silicon substrate containing one or more electronic devices;

forming a first dielectric layer over said silicon substrate;

forming a second dielectric layer over said first dielectric layer wherein the dielectric constant of the second dielectric layer is less than 3.0;

forming a capping layer on said second dielectric layer wherein said capping layer consists of a material selected form the group consisting of titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium nitride (TiN), aluminum nitride (AlN), tantalum aluminide (TaAl), and tantalum aluminum nitride (TaAlN);

forming a trench in said second dielectric; and

filling said trench with a conducting material.

2. The method of claim 1 wherein said second dielectric layer is OSG.

3. The method of claim 1 wherein said conducting material is copper.

4. A method for forming integrated circuit interconnects, comprising:

providing a silicon substrate containing one or more electronic devices;

forming a first dielectric layer over said silicon substrate;

forming a second dielectric layer over said etch stop layer wherein the dielectric constant of the second dielectric layer is less than 3.0;

forming a capping layer on said second dielectric layer wherein said capping layer consists of a material selected form the group consisting of titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium nitride (TiN), aluminum nitride (AlN), tantalum aluminide (TaAl), and tantalum aluminum nitride (TaAlN);

forming a first trench in said second dielectric wherein said first trench has a first width;

forming a second trench in said second dielectric wherein said second trench has a second width different from said first width and said second trench is positioned over said first trench; and

filling said first and second trench with a conducting material.

5. The method of claim 4 wherein said second dielectric layer is OSG.

6. The method of claim 4 wherein said conducting material is copper.