Process for fabricating copper interconnect for ULSI integrated circuits

• US 6,410,435 B1
• Filed: 10/01/1999
• Issued: 06/25/2002
• Est. Priority Date: 10/01/1999
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Guardian Corp. (Broadcom, Inc.)
• Inventors: Ryan, Vivian W.
• Primary Examiner(s): Chaudhari, Chandra
• Assistant Examiner(s): NGUYEN, THANH T
• Application Number:
  US09/410,686
• Time in Patent Office: 998 Days
• Field of Search: 438/687, 438/648, 438/656, 438/683, 438/633, 438/637-640, 438/685, 438/691-692
• US Class Current: 438/687
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48647 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/85375 having an external coating, e.g. protective bond-through coating
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01007 Nitrogen [N]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A method for manufacturing integrated circuits; particularly, a method for fabricating a copper interconnect system and a copper interconnect system, having a layer of CrO, fabricated by the method.

Claims

1. A method of manufacturing an integrated circuit comprising:

a. providing a wafer having an inter-level dielectric film and a barrier layer;

b. depositing a seed layer of copper on said barrier layer;

c. electroplating copper to a thickness sufficient to fill any valleys in said inter-level dielectric film and cover an entire top surface of said wafer;

d. chemical mechanical polishing said top surface to remove i) any excess portions of copper caused by said electroplating and ii) selected portions of said inter-level dielectric film;

e. depositing a layer of CrO on said polished top surface to cover remaining portions of said copper;

f. depositing a passivation layer on said layer of CrO and portions of said inter-level dielectric film; and

g. etching said passivation layer to form a via that exposes a selected portion of said layer of CrO.

2. The method of claim 1 wherein said inter-level dielectric film comprises at least one layer of an inorganic compound selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and mixtures thereof.

3. The method of claim 1 wherein said inter-level dielectric film is SiO₂.

4. The method of claim 1 wherein said inter-level dielectric film comprises at least one layer of an organic compound.

5. The method of claim 1 wherein said barrier layer comprises a material selected from the group consisting of Ta, TaN, TiN, Ti, W, WN, TiSiN, TaSiN, or mixtures thereof.

6. The method of claim 1 wherein said layer of CrO has a thickness of about 150-600 Å

.

7. The method of claim 1 wherein said layer of CrO has a thickness of about 300 Å

.

8. The method of claim 1 wherein said layer of CrO is formed by sputtering Cr in the presence of O₂ and said layer of CrO is patterned using lithography after said layer of CrO is deposited.

9. The method of claim 1 wherein said layer of CrO is formed by evaporating Cr in the presence of O₂ and said layer of CrO is patterned using lithography after said layer of CrO is deposited.

10. The method of claim 1 wherein said layer of CrO is formed by autocatalytic plating Cr in the presence of O₂.

11. The method of claim 1 wherein said barrier layer is backsputtered before said seed layer is formed to improve adhesion.

12. The method of claim 1 wherein said seed layer is formed by sputtering.

13. The method of claim 1 wherein said seed layer is formed by chemical vapor deposition.

14. The method of claim 1 wherein said passivation layer is comprised of a compound selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, doped silicon dioxide, doped silicon nitride, doped silicon oxynitride, and mixtures thereof.

15. The method of claim 1 wherein said passivation layer is formed by a process selected from the group consisting of chemical vapor deposition, spin-on dielectric glass, spin-on dielectric polymer, and combinations thereof.