Method of fabricating semiconductor device

• US 6,410,959 B2
• Filed: 09/21/2001
• Issued: 06/25/2002
• Est. Priority Date: 08/28/1997
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Systems Company Limited (Hitachi, Ltd.)
• Inventors: Oishi, Kentaro, Kudo, Satoshi, Nakazawa, Yoshito, Shigematsu, Takashi, Uesawa, Kozo, Kobayashi, Masayoshi, Imai, Yasuo, Ohnishi, Akihiro, Numazawa, Sumito, Kubo, Sakae
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): KESHAVAN, BELUR V
• Application Number:
  US09/957,041
• Publication Number:
  US 20020009867A1
• Time in Patent Office: 277 Days
• Field of Search: 438/270, 438/212, 438/268, 438/327, 438/342, 257/330, 257/341, 257/342, 257/328
• US Class Current: 257/330
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Claims

1. A metal insulator semiconductor field effect type semiconductor device comprising:

a semiconductor body having first and second main surfaces which are opposite to each other, said first major surface including an element forming region for forming metal insulator semiconductor field effect type elements and a gate lead-out region for forming a gate lead-out electrode of said elements, said gate lead-out region adjoining said element forming region;

a plurality of trench portions extended from one side of said semiconductor body adjoining said gate lead-out region to the other side of said semiconductor body located in said element forming region apart from said gate lead-out region in a first direction from said gate lead-out region to said element forming region, so that said element forming region divided into a plurality of transistor element portions sandwiched between adjacent ones of said plural trench portions, each of said trench portions having a sidewall height from a bottom thereof in said semiconductor body to a top surface of said first major surface;

a first insulation film formed over the sidewall and bottom of each of said trench portions and over the top surface of said first major surface in said gate lead-out region;

an electrode conductive film disposed over said first insulation film so as to fill each of said trench portions with said electrode conductive film, and disposed over the top surface of said major surface in said gate leadout region but leaving said plural transistor element portions uncovered, said electrode conductive film extended, at said one sides of the plural trench portions, from each of said trench portions onto the top surface of said first major surface in said gate lead-out region;

said electrode conductive film having a plurality of first portions which are respectively disposed in said trench portions, each of said first portions having a top surface in each said trench portion at a height from said bottom of each said trench portion, said height of each said first portion is lower than that of said sidewall of each said trench portion, said plurality of first portions of the electrode conductive film serving as gate electrodes, respectively;

said electrode conductive film having a second portion which is extended over the top surface of said first major surface in said gate lead-out region and is formed integrally with said first portions, said second portion of the electrode conductive film serving as a gate lead-out electrode electrically and commonly connected to said first portions of the electrode conductive film;

a second insulation film formed over said electrode conductive film and over said plural transistor element portions, said second insulation film having a first contact hole, which exposes said second portion of the electrode conductive film disposed over said gate lead-out region, and having second contact holes, which expose said plural transistor element portions respectively;

a gate interconnection conductive film overlying said gate lead-out region and contacted with said second portion of the electrode conductive film through said first contact hole of the second insulating film; and

a source interconnection conductive film overlying said element forming region, and contacted with said transistor element portions through said second contact holes of the second insulating film so as to electrically connect said transistor element portions in common, said source interconnection conductive film having portions extended across said trench portions.

2. A semiconductor device according to claim 1, wherein said other sides of the plural trench portions are commonly connected with a second trench portion which is extended in a second direction perpendicular to said first direction, and wherein said second trench portion is filled with said electrode conductive film and is electrically connected to said other sides of the plural trench portions in common.

3. A semiconductor device according to claim 2, wherein said one sides of the plural trench portions are commonly connected with a third trench portion which is extended in the second direction perpendicular to said first direction, and wherein said third trench portion is filled with said electrode conductive film and is electrically connected to said one sides of the plural trench portions in common.

4. A semiconductor device according to claim 3, wherein said plural trench portions and said second and third trench portions define each of said plural transistor element portions as an octagonal shape in plan view.

5. A semiconductor device according to claim 2, further comprising:

a drain electrode conductive film formed on said second major surface of said semiconductor body.

6. A semiconductor device according to claim 5, further comprising:

a third insulating film overlying said gate and source interconnection conductive films, and having bonding openings for exposing portions of said gate and source interconnection conductive films.

7. A semiconductor device according to claim 6, further comprising:

a drain electrode conductive film formed on said second major surface of said semiconductor body.

8. A semiconductor device according to claim 7, wherein each of said transistor element portions comprises:

a channel forming region of one conductivity type extending into the corresponding transistor element portion from said first major surface to such a depth that said channel forming region forms a PN junction with a drain region of the opposite conductivity type which extends from said second major surface of the semiconductor body thereto; and

a source region of said opposite conductivity type formed in said channel forming region and extending to said first major surface.

9. A semiconductor device according to claim 8, wherein said gate conductive film comprises a polycrystalline silicon film, and wherein each of said source and gate interconnection conductive films comprises an aluminum film.