Method for testing a product integrated circuit wafer using a stimulus integrated circuit wafer

• US 6,411,116 B1
• Filed: 08/04/1995
• Issued: 06/25/2002
• Est. Priority Date: 08/31/1994
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: DeHaven, Robert Keith, Wenzel, James F.
• Primary Examiner(s): KARLSEN, ERNEST F
• Application Number:
  US08/511,425
• Time in Patent Office: 2,517 Days
• Field of Search: 324/158.1, 324/757, 324/754, 324/760, 324/765
• US Class Current: 324/762.01
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2849 Environmental or reliability testing, e.g. burn-in or validation tests of individual semiconductors G01R31/2642; of printed circuits boards G01R31/2817; of IC's G01R31/2855
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: G01R 31/2874 related to temperature
• CPC Class Codes: G01R 31/2879 related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads
• CPC Class Codes: G01R 31/2881 related to environmental aspects other than temperature, e.g. humidity or vibrations
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/49128 Assembling formed circuit to base
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49162 by using wire as conductive path

Abstract

A method, apparatus, and circuit distribution wafer (CDW) (16) are used to wafer-level test a product wafer (14) containing one or more product integrated circuits (ICs). The CDW (16) contains circuitry which is used to test the ICs on the product wafers (14). A connection from the product wafer (14) to the CDW (16) is made via a compliant interconnect media (IM) (18). Through IM (18), the CDW (16) tests the product wafer (14) under any set of test conditions. Through external connectors and conductors (20, 22, 24, and 26) the CDW (16) transmits and receives test data, control information, temperature control, and the like from an external tester (104). To improve performance and testability, the CDW (16) and heating/cooling (80 and 82) of the wafers may be segmented into two or more wafer sections for greater control and more accurate testing.

Claims

1. A test circuit comprising:

a first plurality of input terminals and a first plurality of output terminals formed on a semiconductor substrate;

a plurality of buffers coupled between the first plurality of input terminals and the first plurality of output terminals on the semiconductor substrate, a portion of the first plurality of output terminals being coupled to a compliant interconnect media wherein the compliant interconnect media is a dielectric material having a plurality of conductive fibers formed therethrough;

a current sensing and blocking circuit for sensing current through one of the first plurality of inputs and electrically disconnecting the one of the first plurality of inputs from the compliant interconnect media if a predetermined current limit is exceeded, the current sensing and blocking circuit being formed on the semiconductor substrate;

a voltage sensing and blocking circuit for sensing voltage through the one of the first plurality of inputs and electrically disconnecting the one of the first plurality of inputs from the compliant interconnect media if a predetermined voltage limit is exceeded, the voltage sensing and blocking circuit being formed on the semiconductor substrate;

a feedback circuit for receiving data from at least one of the voltage sensing and blocking circuit, the current sensing and blocking circuit, and the plurality of buffers, and using this data to provide test information, the feedback circuit being formed on the semiconductor substrate;

a temperature circuit coupled to the feedback circuit, the temperature circuit being used for receiving and processing temperature information, the feedback circuit being formed on the semiconductor substrate.

2. The test circuit of claim 1 wherein the test circuit further comprises:

test circuitry coupled to the compliant interconnect media for sending functional test signals through the compliant interconnect media.

3. The test circuit of claim 1 wherein the plurality of buffers communicate JTAG information through the compliant interconnect media.

4. Test circuitry formed on an entire semiconductor wafer, the test circuitry comprising:

N test circuits for providing test signals through a compliant interconnect media and for monitoring voltage and current provided through the compliant interconnect media, the N test circuit being subdivided into M distinct groups; and

M feedback circuits, each of the M feedback circuits monitoring temperature information from a unique one of the M distinct groups.

5. The test circuitry of claim 4 wherein the M feedback circuits process binary control information transmitted across the compliant interconnect media.

6. The test circuitry of claim 5 wherein the binary control information indicates if the compliant interconnect media is coupled to a non-functional integrated circuit or a functional integrated circuit.

7. The test circuitry of claim 4 wherein the N test circuits and the M feedback circuits are inter-coupled via a metallic bus structure which spans a substantial portion of a diameter of the semiconductor wafer.

8. The test circuitry of claim 4 wherein the N test circuits provide a clock signal, a reset signal, and a data input signal to the compliant interconnect media and receive a data output signal from the compliant interconnect media.

9. The test circuitry of claim 4 wherein the N test circuits provide a ground supply voltage and a power supply voltage to the compliant interconnect media.

10. The test circuitry of claim 4 wherein the N test circuits test product integrated circuits on a product wafer wherein the product wafer is coupled to the compliant interconnect media.

11. Test circuitry formed across a semiconductor wafer, the test circuitry comprising:

a plurality of test integrated circuits separated by scribe lines, each test integrated circuit in the plurality of integrated circuits having;

a plurality of input terminals and a plurality of output terminals, the plurality of input terminals comprising a reset signal, a clock signal, and a test data input signal;

a plurality of buffers coupled between the plurality of input terminals and the plurality of output terminals which allow the plurality of output terminals to be selectively disconnected from the plurality of input terminals; and

voltage and current blocking circuitry for disconnecting the plurality of input terminals from the plurality of output terminals via the plurality of buffers when one of either a voltage limit or current limit is exceeded in a respective test integrated circuit;

at least one feedback circuit coupled to several test integrated circuits for communicating test and temperature information from the semiconductor wafer to external to the semiconductor wafer; and

a compliant interconnect media coupled to the plurality of outputs, the compliant interconnect media being a dielectric material having a plurality of conductive fibers formed through the dielectric material.

12. The test circuitry of claim 11 wherein a product wafer containing product integrated circuits is coupled to the compliant interconnect media so that the plurality of test integrated circuits test the product integrated circuits through the compliant interconnect media.

13. The test circuitry of claim 11 wherein the at least one feedback circuit contains temperature sensing circuitry which detects a temperature of the test circuitry.

14. The test circuitry of claim 11 wherein the at least one feedback circuit contains a decoder for receiving information from a plurality of the test integrated circuits and communicating this information external to the semiconductor wafer.

15. The test circuitry of claim 11 wherein the compliant interconnect media is in contact with a top layer of metal that is exposed on a top surface of the semiconductor wafer, the top layer of metal being coupled to the test integrated circuits.

16. The test circuitry of claim 11 wherein the plurality of test integrated circuits receive the clock signal, the reset signal, the test data input signal, a power supply voltage, and a ground potential, from a plurality of conductive lines that traverse a substantial portion of the semiconductor wafer.

17. The test circuitry of claim 11 wherein the plurality of test integrated circuits contain MOS transistors wherein all of the MOS transistors are N-channel transistors.

18. The test circuitry of claim 11 wherein a product wafer containing product integrated circuits is coupled to the compliant interconnect media for testing via the test integrated circuits, the at least one feedback circuit communicating to an external tester which of the product integrated circuits are functional and which of the product integrated circuits are non-functional based upon testing performed via the test integrated circuits.

19. The test circuitry of claim 11 wherein test integrated circuits provide phase lock loop (PLL) information through the compliant interconnect media.

20. The test circuitry of claim 11 wherein test integrated circuits level sensitive shift design (LSSD) information through the compliant interconnect media.