Method for testing a product integrated circuit wafer using a stimulus integrated circuit wafer
First Claim
1. A test circuit comprising:
- a first plurality of input terminals and a first plurality of output terminals formed on a semiconductor substrate;
a plurality of buffers coupled between the first plurality of input terminals and the first plurality of output terminals on the semiconductor substrate, a portion of the first plurality of output terminals being coupled to a compliant interconnect media wherein the compliant interconnect media is a dielectric material having a plurality of conductive fibers formed therethrough;
a current sensing and blocking circuit for sensing current through one of the first plurality of inputs and electrically disconnecting the one of the first plurality of inputs from the compliant interconnect media if a predetermined current limit is exceeded, the current sensing and blocking circuit being formed on the semiconductor substrate;
a voltage sensing and blocking circuit for sensing voltage through the one of the first plurality of inputs and electrically disconnecting the one of the first plurality of inputs from the compliant interconnect media if a predetermined voltage limit is exceeded, the voltage sensing and blocking circuit being formed on the semiconductor substrate;
a feedback circuit for receiving data from at least one of the voltage sensing and blocking circuit, the current sensing and blocking circuit, and the plurality of buffers, and using this data to provide test information, the feedback circuit being formed on the semiconductor substrate;
a temperature circuit coupled to the feedback circuit, the temperature circuit being used for receiving and processing temperature information, the feedback circuit being formed on the semiconductor substrate.
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Accused Products
Abstract
A method, apparatus, and circuit distribution wafer (CDW) (16) are used to wafer-level test a product wafer (14) containing one or more product integrated circuits (ICs). The CDW (16) contains circuitry which is used to test the ICs on the product wafers (14). A connection from the product wafer (14) to the CDW (16) is made via a compliant interconnect media (IM) (18). Through IM (18), the CDW (16) tests the product wafer (14) under any set of test conditions. Through external connectors and conductors (20, 22, 24, and 26) the CDW (16) transmits and receives test data, control information, temperature control, and the like from an external tester (104). To improve performance and testability, the CDW (16) and heating/cooling (80 and 82) of the wafers may be segmented into two or more wafer sections for greater control and more accurate testing.
99 Citations
20 Claims
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1. A test circuit comprising:
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a first plurality of input terminals and a first plurality of output terminals formed on a semiconductor substrate;
a plurality of buffers coupled between the first plurality of input terminals and the first plurality of output terminals on the semiconductor substrate, a portion of the first plurality of output terminals being coupled to a compliant interconnect media wherein the compliant interconnect media is a dielectric material having a plurality of conductive fibers formed therethrough;
a current sensing and blocking circuit for sensing current through one of the first plurality of inputs and electrically disconnecting the one of the first plurality of inputs from the compliant interconnect media if a predetermined current limit is exceeded, the current sensing and blocking circuit being formed on the semiconductor substrate;
a voltage sensing and blocking circuit for sensing voltage through the one of the first plurality of inputs and electrically disconnecting the one of the first plurality of inputs from the compliant interconnect media if a predetermined voltage limit is exceeded, the voltage sensing and blocking circuit being formed on the semiconductor substrate;
a feedback circuit for receiving data from at least one of the voltage sensing and blocking circuit, the current sensing and blocking circuit, and the plurality of buffers, and using this data to provide test information, the feedback circuit being formed on the semiconductor substrate;
a temperature circuit coupled to the feedback circuit, the temperature circuit being used for receiving and processing temperature information, the feedback circuit being formed on the semiconductor substrate. - View Dependent Claims (2, 3)
test circuitry coupled to the compliant interconnect media for sending functional test signals through the compliant interconnect media.
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3. The test circuit of claim 1 wherein the plurality of buffers communicate JTAG information through the compliant interconnect media.
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4. Test circuitry formed on an entire semiconductor wafer, the test circuitry comprising:
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N test circuits for providing test signals through a compliant interconnect media and for monitoring voltage and current provided through the compliant interconnect media, the N test circuit being subdivided into M distinct groups; and
M feedback circuits, each of the M feedback circuits monitoring temperature information from a unique one of the M distinct groups. - View Dependent Claims (5, 6, 7, 8, 9, 10)
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11. Test circuitry formed across a semiconductor wafer, the test circuitry comprising:
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a plurality of test integrated circuits separated by scribe lines, each test integrated circuit in the plurality of integrated circuits having;
a plurality of input terminals and a plurality of output terminals, the plurality of input terminals comprising a reset signal, a clock signal, and a test data input signal;
a plurality of buffers coupled between the plurality of input terminals and the plurality of output terminals which allow the plurality of output terminals to be selectively disconnected from the plurality of input terminals; and
voltage and current blocking circuitry for disconnecting the plurality of input terminals from the plurality of output terminals via the plurality of buffers when one of either a voltage limit or current limit is exceeded in a respective test integrated circuit;
at least one feedback circuit coupled to several test integrated circuits for communicating test and temperature information from the semiconductor wafer to external to the semiconductor wafer; and
a compliant interconnect media coupled to the plurality of outputs, the compliant interconnect media being a dielectric material having a plurality of conductive fibers formed through the dielectric material. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification