Self-refresh on-chip voltage generator

• US 6,411,157 B1
• Filed: 06/29/2000
• Issued: 06/25/2002
• Est. Priority Date: 06/29/2000
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hsu, Louis L., Wang, Li-Kong
• Primary Examiner(s): Cunningham, Terry D.
• Application Number:
  US09/606,650
• Time in Patent Office: 726 Days
• Field of Search: 327/534, 327/535, 327/536, 365/226, 365/229
• US Class Current: 327/536
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 2211/4067 Refresh in standby or low power modes
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type

Abstract

A voltage control system and methodology for maintaining internally generated voltage levels in a semiconductor chip. The method comprises the steps of intermittently sampling an internal voltage supply level during a low power or “sleep” mode of operation; comparing the internal voltage supply level against a predetermined voltage reference level; and, activating a voltage supply generator for increasing the internal voltage supply level when the internal voltage supply level falls below the predetermined voltage reference level. The voltage supply generator is subsequently deactivated when the voltage supply level is restored to the predetermined voltage reference level. The sampling cycle may be appropriately tailored according to chip condition, chip temperature, and chip size. In one embodiment, the voltage control system and methodology is implemented in DRAM circuits during a refresh operation. The voltage levels that are suitable for sampling including DRAM band-gap reference voltage, boost wordline line voltage, wordline low voltage, bitline high voltage and bitline equalization voltages.

Claims

1. A voltage control system for an integrated circuit comprising:

voltage supply generator providing a voltage source for internal, on-chip use, said voltage supply generator responsive to a low power enable signal for placing said system in a low power mode, and, said voltage supply generator responsive to an active enable signal for placing said system in an active mode; and

,

a limiter device for intermittently sampling an internal voltage supply level of said voltage source during said low power mode, and continuously sampling said internal voltage supply level during said active mode, and for determining whether a voltage result of said sampling falls below a predetermined voltage reference level, and, when said voltage result of said sampling falls below said predetermined voltage reference level, said limiter device activating said voltage supply generator for increasing said internal voltage supply level, and deactivating said voltage supply generator when said voltage result of said sampling is restored to said predetermined voltage reference level, whereby internally generated voltage levels are maintained throughout system low power and active modes of operation.

2. The voltage control system as claimed in claim 1, wherein said limiter device includes comparator means triggered by a sampling input for comparing said internal voltage supply level with said predetermined voltage reference level.

3. The voltage control system as claimed in claim 1, further comprising a timer circuit which is responsive to said low power enable signal, for generating an intermittent timing signal for controlling said limiter device.

4. The voltage control system as claimed in claim 1, wherein said low power mode of operation includes a sleep mode, said low power enable signal comprising a sleep enable signal for placing said system in said sleep mode.

5. The voltage control system as claimed in claim 3, wherein said timer circuit is responsive to said low power enable signal for generating said intermittent timing signal only during said low power mode.

6. The voltage control system as claimed in claim 3, wherein said intermittent timing signal is periodic.

7. The voltage control system as claimed in claim 3, wherein said intermittent timing signal comprises one or more pulses, said timer circuit further comprising means for modifying a pulse width and period of said one or more pulses based on integrated circuit operating conditions.

8. The voltage control system as claimed in claim 2, wherein said voltage supply generator comprises charge pump for boosting said internal voltage supply level, said charge pump responsive to an output of said comparator means.

9. The voltage control system as claimed in claim 2, further comprising a device for intentionally increasing the sampled voltage supply level during a sampling interval.

10. The voltage control system as claimed in claim 9, wherein an output of said voltage supply generator is sampled through a resistor divider circuit, said device for intentionally increasing output voltage including device for decreasing resistance of said resistor divider circuit at said comparator sampling input.

11. The voltage control system as claimed in claim 1, wherein said voltage supply generator remains deactivated until again activated by an intermittent sampling signal.

12. The voltage control system as claimed in claim 1 wherein said voltage supply generator remains deactivated until again activated by receipt of said active enable signal.

13. A method for controlling internally supplied voltage level generated within an integrated circuit, said method comprising:

a) intermittently sampling said internal voltage supply level during a low-power mode of operation;

b) continuously sampling said internal voltage supply level during an active mode of operation;

c) comparing a voltage result of said sampling of said internal voltage supply level against a predetermined voltage reference level; and

,

d) activating a voltage supply generator for increasing said internal voltage supply level when said voltage result of said sampling falls below said predetermined voltage reference level, and, deactivating said voltage supply generator when said voltage result of said sampling is restored to said predetermined voltage reference level, whereby internally generated voltage levels are maintained throughout system low power and active modes of operation.

14. The method as claimed in claim 13, wherein said step of intermittently sampling comprises the step of generating an intermittent timing signal for controlling a sampling device.

15. The method as claimed in claim 14, wherein said intermittent timing signal is periodic.

16. The method as claimed in claim 14, wherein said intermittent timing signal comprises one or more pulses, a pulse width and period of said one or more pulses being modifiable based on integrated circuit operating conditions.

17. The method as claimed in claim 14, wherein said step of intermittently sampling further comprises the step of increasing the sampled voltage supply level during a sampling interval.

18. The method as claimed in claim 17, wherein an output of said voltage supply generator is sampled through a resistor divider circuit, said step of increasing the sampled voltage supply comprising intentionally bypassing a resistor portion in said resistor divider during said sampling interval.

19. The method as claimed in claim 13, further comprising the step of deactivating said voltage supply generator until again activated by an intermittent sampling signal.

20. The method as claimed in claim 13, further comprising the step of deactivating said voltage supply generator until again activated by receipt of an active enable signal.

21. A self-refresh, on-chip voltage generator system for a semiconductor chip and having one or more voltage supply generators each for providing a respective voltage supply for internal semiconductor chip operation, said system comprising:

a limiter device associated with each said voltage generator and responsive to a respective timing signal for intermittently sampling a voltage supply level of the corresponding voltage generator during a low power mode of operation, and responsive to an active enable signal for continuously sampling a respective voltage supply level during an active mode of operation, and for determining whether said sampled voltage supply level falls below an associated predetermined voltage reference level, wherein when any said sampled voltage supply level falls below its associated predetermined voltage reference level, said limiter device activating a respective said voltage supply generator for increasing said respective voltage supply level, and deactivating said respective voltage supply generator when its respective voltage supply level is restored to its associated predetermined voltage reference level, whereby internally generated voltage levels are maintained throughout said system low power operation and active mode operation.

22. The self-refresh, on-chip voltage generator system for a semiconductor chip as claimed in claim 21, wherein said semiconductor chip comprises one of DRAM, flash memory, microprocessor, SRAM and logic circuits.

23. The self-refresh, on-chip voltage generator system for a semiconductor chip as claimed in claim 22, further comprising on-chip clock signal generator for generating an intermittent timing signal for respective limiter sampling.

24. The self-refresh, on-chip voltage generator system for a semiconductor chip as claimed in claim 23, wherein said on-chip clock signal generator generating a periodic refresh signal for controlling internal chip operation.

25. The self-refresh, on-chip voltage generator system for a semiconductor chip as claimed in claim 24, wherein each said intermittent timing signal for respective limiter sampling comprises said periodic refresh signal.

26. The self-refresh, on-chip voltage generator system for a semiconductor chip as claimed in claim 23, wherein said intermittent timing signal is periodic.

27. The self-refresh, on-chip voltage generator system for a semiconductor chip as claimed in claim 24, wherein said on-chip clock signal generator further comprises means for modifying a pulse width and period of said one or more pulses based on semiconductor chip device operating conditions.

28. The self-refresh, on-chip voltage generator system for a semiconductor chip as claimed in claim 23, wherein each said generated intermittent timing signal for a limiter is generated in accordance with the voltage supply generator voltage it is sampling.

29. The self-refresh, on-chip voltage generator system for a semiconductor chip as claimed in claim 28, wherein each said limiter device comprises mechanism for intentionally increasing a respective sampled voltage supply level during a sampling interval in order to sustain leakage current during system low power mode operation.