Equalization system using general purpose filter architecture

• US 6,411,253 B1
• Filed: 06/14/2000
• Issued: 06/25/2002
• Est. Priority Date: 06/14/2000
• Status: Expired due to Term

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Baker, Robert M., Freeman, Stephen, Cox, Lloyd C., Nunez, Luis R., Krzemien, Cynthia R., Gramlich, Gary A., Neary, Brian P., Krim, Jordan A.
• Primary Examiner(s): Pihulic, Daniel T.
• Application Number:
  US09/593,202
• Time in Patent Office: 741 Days
• Field of Search: 342/195, 342/194, 342/13, 348/607
• US Class Current: 342/194
• CPC Class Codes: G01S 7/285 Receivers
• CPC Class Codes: H03H 17/0294 Variable filters; Programmable filters
• CPC Class Codes: H04N 5/14 Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00

Abstract

An equalization system and method. In a most general sense, the inventive equalization system includes first and second filters for filtering an in-phase component of a received signal in accordance with first and second sets of coefficients, respectively. The system includes third and fourth filters for filtering a quadrature component of the input signal in accordance with third and fourth sets of coefficients, respectively. The outputs of the first and third filters are subtracted to provide an equalized in-phase output signal and the outputs of the second and fourth filters are added to provide an equalized quadrature output signal. In the illustrative embodiment the filters are finite impulse response filters and the coefficients are provided by a microprocessor. In accordance with the present teachings, the filters are implemented in a general purpose filter. The delay elements of the filters are calculated in accordance with a mean square error algorithm. Accordingly, the coefficients are the product of the correlation between inputs to the delay elements and a cross correlation between the inputs and a set of values representative of a desired response.

Claims

1. An equalizer comprising:

first and second filters for filtering an in-phase component of a received signal in accordance with first and second sets of coefficients, respectively, said first and second filters being implemented in a general purpose filter;

third and fourth filters for filtering a quadrature component of said input signal in accordance with third and fourth sets of coefficients, respectively, said third and fourth filters being implemented in a general purpose filter;

first means for subtracting the outputs of said first and third filters to provide an equalized in-phase output signal;

second means for adding the outputs of said second and fourth filters to provide an equalized quadrature output signal; and

means for providing said coefficients.

2. The invention of claim 1 wherein said filters are finite impulse response filters.

4. The invention of claim 1 wherein said means for providing said coefficients is a microprocessor.

5. The invention of claim 4 wherein each finite impulse response filter includes a plurality of delay elements connected in series.

6. The invention of claim 5 wherein the coefficients are calculated in accordance with a mean square error algorithm.

7. The invention of claim 6 wherein the coefficients are the product of the correlation between inputs to said delay elements and a cross correlation between said inputs and a set of values representative of a desired response.

3. An equalization method including the steps of:

filtering an in-phase component of a received signal with first and second filters in accordance with first and second sets of coefficients, respectively first and second filters for filtering an in-phase component of a received signal in accordance with first and second sets of coefficients, respectively, said first and second filters being implemented in a general purpose filter;

filtering a quadrature component of said input signal with third and fourth filters in accordance with third and fourth sets of coefficients, respectively, said third and fourth filters being implemented in a general purpose filter;

subtracting the outputs of said first and third filters to provide an equalized in-phase output signal; and

adding the outputs of said second and fourth filters to provide an equalized quadrature output signal.

8. A digital receiver comprising:

an antenna for receiving a radio frequency signal;

a first signal processor disposed in a first channel for processing said received signal and providing a first baseline signal in response thereto;

a second signal processor disposed in a second channel for processing said received signal and providing a second baseline signal in response thereto;

first analog to digital converter means for processing said first baseline signal and providing a first digitized baseline signal in response thereto;

second analog to digital converter means for processing said second baseline signal and providing a second digitized baseline signal in response thereto; and

means for equalizing said first and second baseline signals, said means for equalizing including first and second equalizers disposed in said first and second channels respectively, each of said equalizers comprising;

first and second filters for filtering an in-phase component of a received signal in accordance with first and second sets of coefficients, respectively,

third and fourth filters for filtering a quadrature component of said input signal in accordance with third and fourth sets of coefficients, respectively,

first means for subtracting the outputs of said first and third filters to provide an equalized in-phase output signal,

second means for adding the outputs of said second and fourth filters to provide an equalized quadrature output signal, and

means for providing said coefficients; and

means for combining the outputs of said first and second equalizers.

9. The invention of claim 8 wherein said filters are finite impulse response filters.

10. The invention of claim 8 wherein said filters are implemented in a general purpose filter.

11. The invention of claim 10 wherein said means for providing said coefficients is a microprocessor.

12. The invention of claim 11 wherein each finite impulse response filters includes a plurality of delay elements connected in series.

13. The invention of claim 12 wherein the coefficients are calculated in accordance with a mean square error algorithm.

14. The invention of claim 13 wherein the coefficients are the product of the correlation between inputs to said delay elements and a cross correlation between said inputs and a set of values representative of a desired response.