Method and apparatus for addressing multiple frame buffers
First Claim
1. A method of addressing a plurality of video memory areas having a predetermined arrangement, as a logical frame buffer comprising the steps of:
- (a) providing a display controller subsystem means which couples a video memory subsystem means to a video device subsystem means via a plurality of video streams;
(b) providing an address translation means which accepts a logical address as an input and responsively generates a translated output for accessing said video memory subsystem means;
(c) locating each of the video memory areas within said video memory subsystem means;
(d) configuring a physical pitch for each of the video memory areas such that said physical pitch corresponds to the difference in video memory addresses between adjacent vertical pixels in the video memory area;
(e) reserving a number of logical address space pages for said logical frame buffer sufficient in size for storing said predetermined arrangement of the video memory areas; and
(f) configuring said address translation means to map the reserved logical address space pages to pages within the video memory areas such that any adjacent vertical pixels in said predetermined arrangement of video memory areas are separated by a constant number of logical addresses, said constant corresponding to a logical pitch for accessing said logical frame buffer, wherein;
each of the video memory areas is coupled to one or more video streams, two or more of the video streams are coupled to distinct video memory areas and have a common video direction;
said display controller subsystem means contains one or more display controllers; and
adjacent vertical pixels correspond to pixels in distinct scan lines.
2 Assignments
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Accused Products
Abstract
High resolution image data is stored in multiple frame buffers to enable the image data to be coupled to multiple lower resolution video streams. Despite physical address discontinuities at frame buffer crossover boundaries, addressing of the multiple frame buffers as a single logical frame buffer is made possible by first dividing the image data into pages using a page size appropriate for both the video mode and arrangement of the physical frame buffers within the high resolution image. Then a pitch is determined for each of the physical frame buffers that enables the alignment of the memory pages at the frame buffer crossovers. Then for video modes utilizing multiple bytes per pixel, the collection of bytes representing the pixels are aligned on the page boundaries at the frame buffer crossovers. Then linear address space is reserved for storing a single high resolution frame buffer. Then address translation hardware is configured to shuffle the mapping of the pages such that the pages within the reserved linear address space are routed to the appropriate pages within the multiple physical frame buffers to create a single high resolution frame buffer when accessed with an appropriate logical pitch.
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Citations
33 Claims
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1. A method of addressing a plurality of video memory areas having a predetermined arrangement, as a logical frame buffer comprising the steps of:
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(a) providing a display controller subsystem means which couples a video memory subsystem means to a video device subsystem means via a plurality of video streams;
(b) providing an address translation means which accepts a logical address as an input and responsively generates a translated output for accessing said video memory subsystem means;
(c) locating each of the video memory areas within said video memory subsystem means;
(d) configuring a physical pitch for each of the video memory areas such that said physical pitch corresponds to the difference in video memory addresses between adjacent vertical pixels in the video memory area;
(e) reserving a number of logical address space pages for said logical frame buffer sufficient in size for storing said predetermined arrangement of the video memory areas; and
(f) configuring said address translation means to map the reserved logical address space pages to pages within the video memory areas such that any adjacent vertical pixels in said predetermined arrangement of video memory areas are separated by a constant number of logical addresses, said constant corresponding to a logical pitch for accessing said logical frame buffer, wherein;
each of the video memory areas is coupled to one or more video streams, two or more of the video streams are coupled to distinct video memory areas and have a common video direction;
said display controller subsystem means contains one or more display controllers; and
adjacent vertical pixels correspond to pixels in distinct scan lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A computer system for addressing a plurality of video memory areas having a predetermined arrangement, as a logical frame buffer comprising:
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(a) a video memory subsystem means which contains the video memory areas;
(b) a display controller subsystem means which couples said video memory subsystem means to a video device subsystem means via a plurality of video streams; and
(c) an address translation means which will;
(1) separate a logical address space into logical address space pages;
(2) accept a logical address as an input and responsively generate a translated output for accessing said video memory subsystem means;
(3) map logical address space pages to pages within the video memory areas such that any adjacent vertical pixels in said predetermined arrangement of video memory areas are separated by a constant number of logical addresses, said constant corresponding to a logical pitch for accessing said logical frame buffer;
wherein each of the video memory areas is coupled to one or more video streams;
wherein two or more of the video streams are coupled to distinct video memory areas and have a common video direction;
wherein said display controller subsystem means contains one or more display controllers; and
wherein adjacent vertical pixels correspond to pixels in distinct scan lines. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. A method of re-allocating memory for a display surface in a display device driver software component when said display surface is positioned such that it spans a plurality of video memory areas comprising the steps of:
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(a) providing a display controller subsystem means which couples the video memory areas to a video device subsystem means via a plurality of video streams;
(b) providing an address translation means which accepts logical addresses as an input and responsively generates a translated output for accessing the video memory areas;
(c) responding to a software application'"'"'s request for said display surface to be created by allocating memory for the surface in an initial surface memory means which is accessible by the software application;
(d) responding to a software application'"'"'s request for said display surface to be positioned by allocating a logical frame buffer to address the video memory areas;
(e) transferring data from said initial surface memory means to the video memory areas; and
(f) modifying a start address value and a pitch value that are associated with said display surface to values that correspond to said logical frame buffer.
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Specification