Nonvolatile memory using flexible erasing methods and method and system for using same

• US 6,411,546 B1
• Filed: 05/05/2000
• Issued: 06/25/2002
• Est. Priority Date: 03/31/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Lexar Media Incorporated (Micron Technology, Inc.)
• Inventors: Keshtbod, Parviz, Estakhri, Petro, Nemazie, Siamack, Assar, Mahmud
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US09/565,517
• Time in Patent Office: 781 Days
• Field of Search: 365/185.11, 365/185.29, 365/218
• US Class Current: 365/185.11
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

An embodiment of the present invention is disclosed to include a nonvolatile memory system for controlling erase operations performed on a nonvolatile memory array comprised of rows and columns, the nonvolatile memory array stores digital information organized into blocks with each block having one or more sectors of information and each sector having a user data field and an extension field and each sector stored within a row of the memory array. A controller circuit is coupled to a host circuit and is operative to perform erase operations on the nonvolatile memory array, the controller circuit erases an identified sector of information having a particular user data field and a particular extension field wherein the particular user field and the particular extension field are caused to be erased separately.

Claims

1. A nonvolatile memory control circuit for controlling erase operations performed on a nonvolatile memory array comprised of rows and columns, the nonvolatile memory array for storing digital information organized into blocks with each block having one or more sectors of information and each sector having a user data field and an extension field, comprising:

a controller circuit, coupled to a host circuit, said controller circuit operative to perform erase operations on the nonvolatile memory array, the controller circuit being operative to erase a particular sector of information within a particular block, said particular sector of information having a particular user data field and a particular extension field wherein the particular user field and the particular extension field are erased separately.

2. A nonvolatile memory control circuit as recited in claim 1 wherein the extension fields of the sectors of the particular block include an address field, the particular block including a first sector and a second sector.

3. A nonvolatile memory control circuit as recited in claim 2 wherein the address field of the first sector is for storing a first address value to identify a block within the nonvolatile memory array.

4. A nonvolatile memory control circuit as recited in claim 3 wherein the second sector includes a second address field for storing a second address value associated with user data information stored in the user data field of the particular block.

5. A nonvolatile memory control circuit as recited in claim 4 wherein the controller circuit for performing a read-modify-write operation on the extension field of the first sector when the corresponding first address field is to be modified.

6. A nonvolatile memory control circuit as recited in claim 2 wherein the extension field of the second sector includes a non-address field having a flag field for storing flag information relating to the status of the particular block.

7. A nonvolatile memory control circuit as recited in claim 3 wherein the first address field includes a virtual physical block address (VPBA) field for storing a VPBA value.

8. A nonvolatile memory control circuit as recited in claim 4 wherein the second address field includes a virtual logical block address (VLBA) field for storing a VLBA value.

9. A nonvolatile memory control circuit as recited in claim 3 wherein the controller circuit for reading the first address field of the particular block for finding a first address value corresponding to a second block having associated therewith a second address matching the address of the particular block.

10. A nonvolatile memory control circuit as recited in claim 1 wherein the extension fields of the sectors of the particular block include an address field, the particular block including a first sector and a second sector wherein the address field of the first sector is for storing a plurality of first address values with one of said plurality including a most recent first address value for identifying a block within the nonvolatile memory within which the corresponding user data is stored.

11. A nonvolatile memory control circuit as recited in claim 10 wherein the second sector includes a second address field for storing a second address value associated with user data information stored in the user data field of the particular block.

12. A nonvolatile memory control circuit as recited in claim 11 wherein when the first address field is to be modified, the controller circuit for identifying the most recent first address field.

13. A nonvolatile memory control circuit as recited in claim 12 wherein the controller circuit for identifying the most recent first address by searching for the first one of said plurality of first address fields to have an erased value and determining the one of said plurality preceding the one having the erased value as being the most recent first address and if none of said plurality of first address fields includes the erased value, determining that the last one of said plurality of first address fields is the most recent first address.

14. A nonvolatile memory control circuit as recited in claim 12 wherein the controller circuit for performing a read-modify-write operation on the extension field of the particular block upon determining that none of said plurality of first address fields includes the erased value.

15. A nonvolatile memory system comprising:

nonvolatile memory array for storing digital information organized in blocks, each block having one or more sectors and each sector having a user data field and an extension field;

control circuit, coupled to the nonvolatile memory array, for controlling operations performed on the nonvolatile memory array and operative to perform erase operations on the nonvolatile memory array, the controller circuit being operative to erase a particular sector of information, said particular sector of information having a particular user data field and a particular extension field wherein the particular user field and the particular extension field are separately erased.

16. A nonvolatile memory system as recited in claim 15 wherein the extension fields of the sectors of the particular block include an address field, the particular block including a first sector and a second sector.

17. A nonvolatile memory system as recited in claim 16 wherein the address field of the first sector is for storing a first address value to identify a block within the nonvolatile memory array.

18. A nonvolatile memory system as recited in claim 17 wherein the second sector includes a second address field for storing a second address value associated with user data information stored in the user data field of the particular block.

19. A nonvolatile memory system as recited in claim 18 wherein the controller circuit for performing a read-modify-write operation on the extension field of the first sector when the corresponding first address field is to be modified.

20. A nonvolatile memory system as recited in claim 16 wherein the extension field of the second sector includes a flag field for storing flag information relating to the status of the particular block.

21. A nonvolatile memory system as recited in claim 17 wherein the first address field includes a virtual physical block address (VPBA) field for storing a VPBA value.

22. A nonvolatile memory system as recited in claim 18 wherein the second address field includes a virtual logical block address (VLBA) field for storing a VLBA value.

23. A nonvolatile memory control circuit as recited in claim 18 wherein the controller circuit for reading the first address field of the particular block for finding a first address value corresponding to a second block having associated therewith a second VLBA matching the address of the particular block.

24. A nonvolatile memory control circuit as recited in claim 15 wherein the extension fields of the sectors of the particular block include an address field and a non-address field, the particular block including a first sector and a second sector wherein the address field of the first sector stores a plurality of first address values with one of said plurality including a most recent first address value for identifying a block within the nonvolatile memory within which the corresponding user data is stored.

25. A nonvolatile memory control circuit as recited in claim 24 wherein the second sector includes a second address field for storing a second address value associated with user data information stored in the user data field of the particular block.

26. A nonvolatile memory control circuit as recited in claim 25 wherein when the first address field is to be modified, the controller circuit for identifying the most recent first address field.

27. A nonvolatile memory control circuit as recited in claim 26 wherein the controller circuit for identifying the most recent first address by searching for the first one of said plurality of first address fields to have an erased value and determining that the one of said plurality preceding the one having the erased value as being the most recent first address and if none of said plurality of first address fields includes the erased value, determining that the last one of said plurality of first address fields is the most recent first address.

28. A nonvolatile memory system comprising:

host circuit for generating commands;

nonvolatile memory array for storing digital information organized in blocks, each block having one or more sectors and each sector having a user data field and an extension field; and

controller circuit, coupled to the nonvolatile memory array and to the host circuit for receiving host commands and operative to perform erase operations on the nonvolatile memory array, the controller circuit being further operative to erase a particular sector of information, said particular sector of information having a particular user data field and a particular extension field wherein the particular user field and the particular extension field are erased separately.

29. A nonvolatile memory system as recited in claim 28 including a host interface for coupling the controller circuit to the host circuit.

30. A nonvolatile memory device comprising:

nonvolatile memory array for storing digital information, said nonvolatile memory array being organized into blocks, each block having one or more sectors and each sector having a user data field and an extension field, wherein said user data fields of said nonvolatile memory array are formed in a separate well than the extension fields thereby erasing the extension field of a particular sector separately from the user data field of the particular sector.

31. A nonvolatile memory device as recited in claim 30 including a control circuitry coupled to said memory array for controlling same.

32. A method for operating a nonvolatile memory array comprising:

organizing the nonvolatile memory array into blocks, each block having one or more sectors and each sector having a user data field and an extension field;

storing user data into a particular user data field and extension data into a particular extension field of a particular sector of said organized nonvolatile memory array; and

erasing the particular user data field and the particular extension field separately.

33. A method for operating a nonvolatile memory array as recited in claim 32 including the steps of:

searching for a free block;

finding a free block;

modifying a portion of an extension field of a particular sector while preserving the remaining portion of the extension field of the particular sector;

storing user data in the user data field of one of the sectors of the free block; and

performing a read-modify-write operation on the extension field of the sector of the free block including the stored user data.

34. A method for operating a nonvolatile memory array as recited in claim 33 including the step of performing a read-modify-write operation on the extension field of the particular.

35. A method for operating a non-volatile memory array having a plurality of nonvolatile storage blocks for storing data, each block having one or more sectors and each sector including a user data field and an extension field, wherein each block is selectively programmable and erasable wherein only blocks containing no data may be programmed, the method comprising the steps of:

determining whether any blocks having superseded data remain;

periodically selecting blocks having superseded data for erasure thereof; and

erasing the selected blocks wherein the user data fields of the selected blocks is erased separately from the extension fields of the selected blocks.

36. A method for erasing a nonvolatile memory array as recited in claim 35 further including the step of correlating a logical address assigned to a block of superseded data to a physical address of a corresponding block of updated data.

37. A method for erasing a nonvolatile memory array as recited in claim 36 wherein performing said step of correlating within the nonvolatile memory array.

38. A method for operating a nonvolatile memory unit comprising:

organizing the nonvolatile memory unit into blocks, each block having one or more sectors and each sector having a user data field and an extension field;

receiving data having associated therewith a logical address for storage into the nonvolatile memory array;

corresponding the logical address with a physical address within the nonvolatile memory unit; and

storing the received data in a block within the nonvolatile memory unit identified by the physical address.

39. A nonvolatile memory device comprising:

nonvolatile memory array for storing digital information, said nonvolatile memory array being organized into blocks, each block having one or more sectors and each sector having a user data field and an extension field, wherein the user data field and the extension field of a particular sector are erased separately.

40. A nonvolatile memory device as recited in claim 39 wherein said user data fields of said nonvolatile memory array are formed in a separate well than the extension fields.