Semiconductor memory device capable of reducing leakage current flowing into substrate

• US 6,411,560 B1
• Filed: 11/14/2001
• Issued: 06/25/2002
• Est. Priority Date: 06/22/2001
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubishi Electric Engineering Co Ltd (Mitsubishi Electric Corporation)
• Inventors: Hidaka, Hideto, Kato, Hiroshi, Ishikawa, Masatoshi, Tomishima, Shigeki, Tanizaki, Hiroaki, Ooishi, Tsukasa, Tsuji, Takaharu, Maruta, Masanao, Niiro, Mitsutaka
• Primary Examiner(s): Tran, Andrew Q.
• Application Number:
  US09/987,277
• Time in Patent Office: 223 Days
• Field of Search: 365/227, 365/226, 365/189.09, 365/189.02, 365/189.11, 365/189.07, 365/190
• US Class Current: 365/227
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 5/146 Substrate bias generators G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A first power supply voltage is supplied to a power supply node of a sense amplifier. A bit line driver outputs a column select signal composed of a second power supply voltage to the gate terminals of N channel MOS transistors of a GIO line gate circuit. When input/output data is [1], a third power supply voltage lower than the first power supply voltage is supplied onto a global data line. In this case, with a threshold voltage of N channel MOS transistors used, a relation is established: second power supply voltage≦third power supply voltage+threshold voltage. As a result, a leakage current can be reduced in a semiconductor memory device driven by plural power supply voltages with respective different voltage levels.

Claims

1. A semiconductor memory device comprising:

plural memory cells;

plural bit line pairs, provided correspondingly to said plural memory cells, and each for inputting or outputting data to or from a memory cell;

plural sense amplifiers, provided correspondingly to said plural bit line pairs, and each supplying a first power supply voltage to one of a corresponding bit line pair when data is inputted to or outputted from said memory cell;

plural global data line pairs provided correspondingly to said plural bit line pairs;

a write/read circuit supplying a second power supply voltage lower than said first power supply voltage to one of a corresponding global data line pair when data is written onto said memory cell, and receiving said second power supply voltage from said one of said corresponding global data line pair when data is read from said memory cell;

a column decoder circuit outputting an activation signal for activating a bit line pair provided correspondingly to a memory cell to or from which data is inputted or outputted among said plural bit line pairs when data is inputted to or outputted from said memory cell, and a deactivation signal for deactivating bit line pairs provided correspondingly to memory cells other than said memory cell to or from which data is inputted or outputted; and

plural gate circuits provided correspondingly to said plural bit line pairs and said plural global data line pairs,

wherein each of said plural gate circuits connects a corresponding bit line pair to a corresponding global data line pair when receiving said activation signal, while disconnecting a corresponding bit line pair from a corresponding global data line pair when receiving said deactivation signal, and a current flowing from said bit line pair toward said global data line pair through a gate circuit receiving said activation signal is smaller than a predetermined value.

2. The semiconductor memory device according to claim 1, wherein said activation signal is composed of a third power supply voltage and each of said plural gate circuits includes MOS transistors to be activated by said third power supply voltage.

3. The semiconductor memory device according to claim 2, wherein each of said plural gate circuits includes:

a first MOS transistor connected to one of a global data line pair at a source terminal thereof and to one of a bit line pair at a drain terminal thereof, and receiving said third power supply voltage at a gate terminal thereof; and

a second MOS transistor connected to the other of said global data line pair at a source terminal thereof and to the other of said bit line pair at a drain terminal thereof, and receiving said third power supply voltage at a gate terminal thereof,

wherein when threshold voltages of said first and second MOS transistors are Vth, said second power supply voltage is Vcc and said third power supply voltage is VccP by definition, a relation VccP≦

Vcc+Vth is satisfied.

4. The semiconductor memory device according to claim 2, wherein each of said plural gate circuits includes:

a first MOS transistor of a first conductive type, connected to one of a global data line pair at a source terminal thereof and to one of a bit line pair at a drain terminal thereof, and receiving said third power supply voltage at a gate terminal thereof; and

a second MOS transistor of said first conductive type, connected to the other of said global data line pair at a source terminal thereof and to the other of said bit line pair at a drain terminal thereof, and receiving said third power supply voltage at a gate terminal thereof and

said write/read circuit includes a third MOS transistor of a second conductive type,

wherein when threshold voltages of said first and second MOS transistors are Vth, said second power supply voltage is Vcc, said third power supply voltage is VccP and a built-in potential of said third MOS transistor is Vb by definition, a relation VccP≦

Vcc+Vth+Vb is satisfied.

5. The semiconductor memory device according to claim 1, wherein said activation signal is composed of a third power supply voltage generated in response to a voltage level of said second power supply voltage.

6. The semiconductor memory device according to claim 5, further comprising:

a power supply voltage change-over circuit receiving a voltage level change-over signal for changing voltage levels of said third power supply voltage therebetween in response to the voltage level of said second power supply voltage to change over voltage levels of said third power supply voltage based on thus received voltage change-over signal and output said third power supply voltage with a changed voltage level to said column decoder circuit, wherein said column decoder circuit generates said activation signal composed of said third power supply voltage outputted by said power supply change-over circuit.

7. The semiconductor memory device according to claim 6, wherein each of said plural gate circuits includes:

a first MOS transistor connected to one of a global data line pair at a source terminal thereof and to one of a bit line pair at a drain terminal thereof, and receiving said third power supply voltage at a gate terminal thereof; and

a second MOS transistor connected to the other of said global data line pair at a source terminal thereof and to the other of said bit line pair at a drain terminal thereof, and receiving said third power supply voltage at a gate terminal thereof,

wherein when threshold voltages of said first and second MOS transistors are Vth, said second power supply voltage is Vcc and said third power supply voltage is VccP by definition, a relation VccP≦

Vcc+Vth is satisfied.

8. The semiconductor memory device according to claim 6, wherein each of said plural gate circuits includes:

a first MOS transistor of a first conductive type, connected to one of a global data line pair at a source terminal thereof and to one of a bit line pair at a drain terminal thereof, and receiving said third power supply voltage at a gate terminal thereof; and

a second MOS transistor of said first conductive type, connected to the other of said global data line pair at a source terminal thereof and to the other of said bit line pair at a drain terminal thereof, and receiving said third power supply voltage at a gate terminal thereof and

said write/read circuit includes a third MOS transistor of a second conductive type,

wherein when threshold voltages of said first and second MOS transistors are Vth, said second power supply voltage is Vcc, said third power supply voltage is VccP and a built-in potential of said third MOS transistor is Vb by definition, a relation VccP≦

Vcc+Vth+Vb is satisfied.

9. The semiconductor memory device according to claim 6, wherein said power supply voltage change-over circuit changes over voltage levels of said third power supply voltage based on a mode change-over signal.

10. The semiconductor memory device according to claim 6, wherein said power supply voltage change-over circuit changes over voltage levels of said third power supply voltage by means of changing wire bonding or changing masks.

11. The semiconductor memory device according to claim 6, wherein said power supply voltage change-over circuit receives said voltage level change-over signal from a decoding circuit changing modes.

12. The semiconductor memory device according to claim 5, further comprising:

a power supply voltage change-over circuit changing voltage levels of said third power supply voltage with reference to a reference voltage whose voltage level changes in response to the voltage level of said second power supply voltage.

13. The semiconductor memory device according to claim 12, wherein said power supply voltage change-over circuit includes:

a reference voltage generation circuit generating plural reference voltages;

a select circuit selecting said reference voltage according to the voltage level of said second power supply voltage among said plural reference voltages; and

a step-down circuit reducing an external power supply voltage down to said selected reference voltage to generate said third power supply voltage.

14. The semiconductor memory device according to claim 12, wherein said power supply voltage change-over circuit includes:

a reference voltage generation circuit generating said reference voltage with a different voltage level by changing a voltage division ratio for an external power supply voltage in response to the voltage level of said second power supply voltage; and

a step-down circuit reducing said external power supply voltage down to said reference voltage received from said reference voltage generation circuit to generate said third power supply voltage.

15. A semiconductor memory device comprising:

plural power supply terminals for supplying plural power supply voltages with different voltage levels;

plural ground terminals for supplying plural ground voltages with different voltage levels; and

plural circuits using an output node commonly therebetween, and for inputting or outputting data to or from a memory cell,

wherein each of said plural circuits is different from the other in drive voltage and includes a MOS transistor of a first conductive type provided between a power supply node and said output node; and

a MOS transistor of a second conductive type provided between said output node and a ground node,

said MOS transistor of a first conductive type receiving a power supply voltage with the highest voltage level among said plural power supply voltages as a substrate voltage thereof from said power supply terminal, and

said MOS transistor of a second conductive type receiving a ground voltage with the lowest voltage level among said plural ground voltages as a substrate voltage thereof from said ground terminal.

16. The semiconductor memory device according to claim 15, wherein said power supply voltage with the highest voltage level coincides with a voltage supplied to a power supply node of a circuit whose drive voltage is the highest among said plural circuits, and

said ground voltage with the lowest voltage level coincides with a voltage supplied to a ground node of a circuit whose drive voltage is the highest among said plural circuit.

17. The semiconductor memory device according to claim 16, further comprising:

a first switch selecting said power supply voltage with the highest voltage level among said plural power supply voltages to give the selected power supply voltage to said MOS transistor of a first conductive type; and

a second switch selecting said ground voltage with the lowest voltage level among said plural ground voltages to give the selected ground voltage to said MOS transistor of a second conductive type.

18. The semiconductor memory device according to claim 16, further comprising:

a first comparison circuit comparing voltage levels of said plural power supply voltages therebetween to output a result of the comparison;

a second comparison circuit comparing voltage levels of said plural ground voltages therebetween to output a result of the comparison;

a first switch selecting said power supply voltage with the highest voltage level based on said result of the comparison from said first comparison circuit to give the selected power supply voltage to said MOS transistor of a first conductive type; and

a second switch selecting said ground voltage with the lowest voltage level based on said result of the comparison from said second comparison circuit to give the selected ground voltage to said MOS transistor of a second conductive type.

19. The semiconductor memory device according to claim 15, further comprising:

a power supply voltage supply circuit selecting said power supply voltage with the highest voltage level based on voltage levels of said plural power supply voltages to give the selected power supply voltage to said MOS transistor of a first conductive type; and

a ground voltage supply circuit selecting said ground voltage with the lowest voltage level based on voltage levels of said plural ground voltages to give the selected ground voltage to said MOS transistor of a second conductive type.