Coherency protocol

• US 6,412,047 B2
• Filed: 10/01/1999
• Issued: 06/25/2002
• Est. Priority Date: 10/01/1999
• Status: Expired due to Term

• Current Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Shimizu, D., Jones, Andrew
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): ELMORE, STEPHEN C
• Application Number:
  US09/411,453
• Publication Number:
  US 20020019913A1
• Time in Patent Office: 998 Days
• Field of Search: 711/141, 711/146, 711/147, 711/159, 711/129, 711/133
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0835 for main memory peripheral accesses (e.g. I/O or DMA)

Abstract

A computer system having a memory system where at least some of the memory is designated as shared memory. A transaction-based bus mechanism couples to the memory system and includes a cache coherency transaction defined within its transaction set. A processor having a cache memory is coupled to the memory system through the transaction based bus mechanism. A system component coupled to the bus mechanism includes logic for specifying cache coherency policy. Logic within the system component initiates a cache transaction according to the specified cache policy on the bus mechanism. Logic within the processor responds to the initiated cache transaction by executing a cache operation specified by the cache transaction.

Claims

1. A computer system comprising:

a memory system where at least some of the memory is designated as shared memory;

a transaction-based bus mechanism coupled to the memory system wherein the bus mechanism includes a cache coherency transaction defined within its transaction set;

a processor having a cache memory, the processor coupled to the memory system through the transaction based bus mechanism;

a system component coupled to the bus mechanism, the system component including logic for specifying cache coherency policy;

logic within the system component for initiating a cache transaction according to the specified cache policy on the bus mechanism; and

logic within the processor responsive to the initiated cache transaction for executing a cache operation specified by the cache transaction.

2. The computer system of claim 1 further comprising logic within the system component for defining two or more cache partitions having independent cache policies specified for each partition.

3. The computer system of claim 2 wherein the logic for defining two or more cache partitions comprises:

a first register having an entry for each defined cache partition, each entry holding a reference memory address;

a second register having an entry holding a value indicating a size of a range of addresses around the reference memory addresses that comprise each cache partition.

4. The computer system of claim 1 further comprising logic within the processor for generating a response addressed to the system component on the bus mechanism wherein the response acknowledges completion of the cache operation.

5. The computer system of claim 1 wherein the logic for specifying cache coherency policy comprises:

a first register having an entry holding a reference memory address;

a second register having an entry holding a value indicating the specified cache policy for any cache line representing the reference memory address in the cache memory.

6. The computer system of claim 5 wherein the logic for specifying cache coherency policy further comprises a third register having an entry holding a value indicating a range of memory addresses about the reference memory address to which the specified cache policy applies.

7. A method for managing a cache memory accessible by a processor, the method comprising:

specifying a cache coherency policy in a remote system component;

coupling the remote system component to the processor using a transaction-based system bus;

initiating a cache coherency transaction according to the specified coherency policy using the remote system component, the cache coherency transaction being transmitted to the processor on the system bus; and

in response to the initiated cache coherency transaction, causing the processor to perform a cache coherency operation specified by the cache coherency transaction.

8. The method of claim 7 further comprising a step of defining two or more cache partitions having independent cache policies specified for each partition.

9. The method of claim 7 further comprising generating a response message using the processor after the cache coherency operation is performed, the response being addressed to the remote system component.

10. The method of claim 7 further comprising:

storing a reference memory address in the remote system component;

storing a value indicating the specified cache policy in the remote system component, wherein the value indicates the cache policy for a cache line including the reference memory address.

11. The method of claim 10 further comprising:

storing in the remote system component a value indicating a range of addressees about the reference memory address to which the specified cache policy applies.

12. A component for a computer system having a cache memory accessible through a data processor, the component comprising:

an interface for coupling to a system bus to communicate with the data processor and external memory;

logic for specifying cache coherency policy; and

logic for initiating a cache transaction according to the specified cache policy on the bus mechanism, wherein the initiating logic is configured such that the cache transaction is initiated prior to any corresponding direct access to the external memory.

13. The component of claim 12 further comprising logic defining two or more cache partitions having independent cache policies specified for each partition.

15. The component of claim 12, wherein the specifying logic selects the cache coherency policy from a transaction set of cache transaction primitives.

16. The component of claim 15, wherein the specifying logic and the initiating logic are adapted to process requests to a single address in the external memory in an order of receipt from the interface.

14. A component for a computer system having a cache memory accessible through a data processor, the component comprising:

an interface for coupling to a system bus to communicate with the data processor;

logic for specifying cache coherency policy wherein the logic for specifying cache coherency policy further comprises;

a first register having an entry holding a reference memory address;

a second register having an entry holding a value indicating the specified cache policy for any cache line representing the reference memory address in the cache memory; and

logic for initiating a cache transaction according to the specified cache policy on the bus mechanism.

17. A data processor comprising:

a cache memory;

an interface to a system bus; and

a cache control mechanism responsive to cache commands received on the system bus from the interface to map the cache commands onto a cache transaction selected from a transaction set, wherein the cache commands are processed sequentially in order of receipt.

18. The data processor of claim 17, wherein the transaction set includes flush and purge cache transactions.

19. The data processor of claim 17, further including a core adapted to respond to the mapped cache transaction by implementing the cache commands.