Radio frequency identification transponder integrated circuit having a serially loaded test mode register

• US 6,412,086 B1
• Filed: 06/01/1999
• Issued: 06/25/2002
• Est. Priority Date: 06/01/1998
• Status: Expired due to Term

• Current Assignee: Intermec IP Corporation (Honeywell International Inc.)
• Original Assignee: Intermec IP Corporation (Honeywell International Inc.)
• Inventors: Friedman, Daniel J., Dieska, David E.
• Primary Examiner(s): Chung, Phung M.
• Assistant Examiner(s): Torres, Joseph D.
• Application Number:
  US09/323,429
• Time in Patent Office: 1,120 Days
• Field of Search: 714/712-745, 714/726-731, 714/718-723
• US Class Current: 714/733
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G06K 7/0095 Testing the sensing arrangement, e.g. testing if a magnetic card reader, bar code reader, RFID interrogator or smart card reader functions properly testing of electrical circuits G01R31/28

Abstract

A radio frequency identification (RFID) transponder (tag) integrated circuit includes “on-chip” test circuitry. The test circuitry includes a serially-loaded test register. The test register controls the execution of on-chip tests. Such tests may include the testing of EEPROM circuitry included within the IC, the testing of analog circuitry, or the testing of digital circuitry included within the IC.

Claims

1. A radio-frequency identification transponder (RFID tag) integrated circuit (IC) comprising:

a front end processor for processing received radio frequency (RF) signals;

a signal processor for producing a return signal; and

a serially loaded test mode register configured to control the selection of tests to be performed upon the tag IC.

2. The RFID tag IC of claim 1 wherein the tag IC includes a digital test section operated under control of entries within the test mode register.

3. The RFID tag IC of claim 2 wherein the digital test section includes partial scan test circuitry.

4. The RFID tag IC of claim 2 wherein the tag IC includes a data path and control logic and the partial scan test circuitry is responsive to input from the test mode register by testing the IC data path and control logic.

5. The RFID tag IC of claim 4 wherein the RFID tag IC further includes digital clock recovery and data recovery circuitry and the test register enables testing of the digital clock recovery and data recovery circuitry.

6. The RFID tag IC of claim 2 wherein the tag IC further comprises EEPROM circuitry in communication with said front end and the test mode register enables tests which access the EEPROM circuitry through a path other than the front end.

7. The RFID tag IC of claim 6 wherein test circuitry within the IC is responsive to manipulation of the test register by enabling testing of the write margin of the EEPROM.

8. The RFID tag IC of claim 6 wherein test circuitry with the IC is responsive to manipulation of the test register by enabling the performance of a bulk even test on the EEPROM.

9. The RFID tag IC of claim 6 wherein test circuitry within the IC is responsive to manipulation of the test register by enabling the performance of a bulk odd test on the EEPROM.

10. The RFID tag IC of claim 6 wherein test circuitry within the tag IC is responsive to manipulation of the test register by enabling the performance of a bulk lock test on the EEPROM.

11. The RFID tag IC of claim 6 wherein test circuitry within the tag IC is responsive to manipulation of the test register by enabling the performance of one or more EEPROM control verification tests.

12. The RFID tag IC of claim 2 further comprising an analog circuit section and test circuitry responsive to manipulation of the test register by enabling the testing of circuit parametrics.

13. The RFID tag IC of claim 12 wherein circuit parametrics include the IC'"'"'s current drain.

14. The RFID tag IC of claim 12 wherein circuit parametrics include the IC'"'"'s bias levels.

15. The RFID tag IC of claim 1 further including memory and test circuitry responsive to a calibrate command by scrolling out the contents of the memory.

16. An RFID tag comprising:

an antenna; and

an RFID IC responsive to signals received at the antenna, the RFID IC including;

a front end processor for processing received radio frequency (RF) signals;

a signal processor for producing a return signal; and

a serially loaded test mode register configured to control the selection of tests to be performed upon the tag IC.

17. The RFID tag of claim 16 wherein the tag IC includes a digital test section operated under control of entries within the test mode register.

18. The RFID tag of claim 17 wherein the digital test section includes partial scan test circuitry.

19. The RFID tag of claim 17 herein the tag IC includes a data path and control logic and the partial scan test circuitry is responsive to input from the test mode register by testing the IC data path and control logic.

20. The RFID tag of claim 19 wherein the RFID tag IC further includes digital clock recovery and data recovery circuitry and the test register enables testing of the digital clock recovery and data recovery circuitry.

21. The RFID tag of claim 18 wherein the tag IC further comprises EEPROM circuitry in communication with said front end and the test mode register enables tests which access the EEPROM circuitry through a path other than the front end.

22. The RFID tag of claim 21 wherein test circuitry within the IC is responsive to manipulation of the test register by enabling testing of the write margin of the EEPROM.

23. The RFID tag of claim 21 wherein test circuitry with the IC is responsive to manipulation of the test register by enabling the performance of a bulk even test on the EEPROM.

24. The RFID tag of claim 21 wherein test circuitry within the IC is responsive to manipulation of the test register by enabling the performance of a bulk odd test on the EEPROM.

25. The RFID tag of claim 21 wherein test circuitry within the tag IC is responsive to manipulation of the test register by enabling the performance of a bulk lock test on the EEPROM.

26. The RFID tag of claim 21 wherein test circuitry within the tag IC is responsive to manipulation of the test register by enabling the performance of one or more EEPROM control verification tests.

27. The RFID tag of claim 17 further comprising an analog circuit section and test circuitry responsive to manipulation of the test register by enabling the testing of circuit parametrics.

28. The RFID tag of claim 27 wherein circuit parametrics include the IC'"'"'s current drain.

29. The RFID tag of claim 27 wherein circuit parametrics include the IC'"'"'s bias levels.

30. An RFID system comprising:

an RFID tag, inluding

an antenna; and

an RFID IC responsive to signals received at the antenna, the RFID IC including;

a front end processor for processing received radio frequency (RF) signals;

a signal processor for producing a return signal; and

a serially loaded test mode register configured to control the selection of tests to be performed upon the tag IC; and

an RFID base station configured to communicate with the RFID tag.