Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture

• US 6,413,802 B1
• Filed: 10/23/2000
• Issued: 07/02/2002
• Est. Priority Date: 10/23/2000
• Status: Expired due to Term

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Lee, Wen-Chin, Chang, Leland, Choi, Yang-Kyu, Lindert, Nick, Kedzierski, Jakub Tadeusz, Huang, Xuejue, Subramanian, Vivek, Hu, Chenming, King, Tsu-Jae, Bokor, Jeffrey
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Dang, Phuc T.
• Application Number:
  US09/695,532
• Time in Patent Office: 617 Days
• Field of Search: 438/151, 438/157, 438/201, 438/223, 438/241, 438/258, 438/279, 438/283, 438/437, 438/588, 438/594, 438/259, 438/270, 438/303, 438/305, 438/589, 438/592
• US Class Current: 438/151
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A FinFET device is fabricated using conventional planar MOSFET technology. The device is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin. Double gates are provided over the sides of the channel to provide enhanced drive current and effectively suppress short channel effects. A plurality of channels can be provided between a source and a drain for increased current capacity. In one embodiment two transistors can be stacked in a fin to provide a CMOS transistor pair having a shared gate.

Claims

1. A method of fabricating a double gate MOSFET device comprising the steps of:

a) providing a silicon on insulator (SOI) substrate with a first silicon layer overlying an insulating layer and having an exposed major surface,

b) providing an etchant mask on the major surface,

c) patterning the etchant mask to define source, drain, and channel regions and expose surrounding portions of the silicon layer,

d) etching the exposed silicon layer and forming source, drain, and channel regions extending from the insulator layer, the channel being a fin with a top surface and two opposing sidewalls,

e) forming a gate dielectric on sidewalls of the channel region,

f) depositing gate material over the etchant mask and the gate dielectric,

g) selectively masking and etching the gate material to form a gate on the top surface and sidewalls of the channel region and separated from the channel region by the gate dielectric and the etchant mask,

h) forming dielectric spacers between the gate and the source and drain regions, and

i) doping the source and drain regions.

3. The method as defined by claim 1 wherein the silicon layer is lightly doped.

16. The method as defined by claim 1 wherein step c) defines a plurality of channel regions between the source and drain regions.

2. A method of fabricating a double gate MOSFET device comprising the steps of:

a) providing a silicon on insulator (SOI) substrate with a first undoped silicon layer overlying an insulating layer and having an exposed major surface,

b) providing an etchant mask on the major surface,

c) patterning the etchant mask to define source, drain, and channel regions and expose surrounding portions of the silicon layer,

d) etching the exposed silicon layer and forming source, drain, and channel regions extending from the insulator layer,

e) forming a gate dielectric on sidewalls of the channel region,

f) depositing gate material over the etchant mask and the gate dielectric,

g) selectively masking and etching the gate material to form a gate on the sidewalls of the channel region and separated from the channel region by the gate dielectric and the etchant mask,

h) forming dielectric spacers between the gate and the source and drain regions, and

i) doping the source and drain regions.

4. A method of fabricating a double gate MOSFET device comprising the steps of:

a) providing a silicon on insulator (SOI) substrate with a first silicon layer overlying an insulating layer and having an exposed major surface,

b) providing an etchant mask on the major surface,

c) patterning the etchant mask to define source, drain, and channel regions and expose surrounding portions of the silicon layer,

d) etching the exposed silicon layer and forming source, drain, and channel regions extending from the insulator layer,

e) forming a gate dielectric on sidewalls of the channel region,

f) depositing gate material over the etchant mask and the gate dielectric,

g) selectively masking and etching the gate material to form a gate on the sidewalls of the channel region and separated from the channel region by the gate dielectric and the etchant mask, and forming a lightly doped drain extension in the channel between the gate and the drain region,

h) forming dielectric spacers between the gate and the source and drain regions, and

i) doping the source and drain regions.

5. A method of fabricating a double gate MOSFET device comprising the steps of:

a) providing a silicon on insulator (SOI) substrate with a first silicon layer overlying an insulating layer and having an exposed major surface,

b) providing an etchant mask on the major surface,

c) patterning the etchant mask to define source, drain, and channel regions and expose surrounding portions of the silicon layer,

d) etching the exposed silicon layer and forming source, drain, and channel regions extending from the insulator layer,

e) forming a gate dielectric on sidewalls of the channel region,

f) depositing undoped polysilicon gate material over the etchant mask and the gate dielectric,

g) selectively masking and etching the gate material to form a gate on the sidewalls of the channel region and separated from the channel region by the gate dielectric and the etchant mask,

h) forming dielectric spacers between the gate and the source and drain regions, and

i) doping the gate, source and drain regions.

6. The method as defined by claim 5 wherein step (i) includes angled shallow ion implantation to limit amorphizing of the source and drain regions.

7. The method as defined by claim 6 and further including the step of annealing the source and drain regions after ion implantation.

8. The method as defined by claim 7 and further including the step of:

j) applying conductive straps across and in contact with the source and drain regions.

9. The method as defined by claim 8 wherein step (j) includes removing the etchant mask from over the source and drain regions prior to applying conductive straps.

10. A method of fabricating a double gate MOSFET device comprising the steps of:

a) providing a silicon on insulator (SOI) substrate with a first silicon layer overlying an insulating layer and having an exposed major surface,

b) providing an etchant mask on the major surface,

c) patterning the etchant mask to define source, drain, and channel regions and expose surrounding portions of the silicon layer,

d) etching the exposed silicon layer and forming source, drain, and channel regions extending from the insulator layer,

e) forming a gate dielectric on sidewalls of the channel region,

f) depositing gate material over the etchant mask and the gate dielectric,

g) selectively masking and etching the gate material to form a gate on the sidewalls of the channel region and separated from the channel region by the gate dielectric and the etchant mask,

h) forming dielectric spacers between the gate and the source and drain regions, and

i) doping the source and drain regions by angled shallow ion implantation to limit amorphizing the source and drain regions.

11. The method as defined by claim 10 and further including the step of annealing the source and drain regions after ion implantation.

12. The method as defined by claim 11 and further including the step of:

j) applying conductive straps across and in contact with the source and drain regions.

13. The method as defined by claim 12 wherein step j) includes removing the etchant mask from over the source and drain regions prior to applying conductive straps.

14. A method of fabricating a double gate MOSFET device comprising the steps of:

a) providing a silicon on insulator (SOI) substrate with a first silicon layer overlying an insulating layer and having an exposed major surface,

b) providing an etchant mask on the major surface,

c) patterning the etchant mask to define source, drain, and channel regions and expose surrounding portions of the silicon layer,

d) etching the exposed silicon layer and forming source, drain, and channel regions extending from the insulator layer,

e) forming a gate dielectric on sidewalls of the channel region,

f) depositing gate material over the etchant mask and the gate dielectric,

g) selectively masking and etching the gate material to form a gate on the sidewalls of the channel region and separated from the channel region by the gate dielectric and the etchant mask,

h) forming dielectric spacers between the gate and the source and drain regions,

i) doping the source and drain regions, and

j) applying conductive straps across and in contact with the source and drain regions.

15. The method as defined by claim 14 wherein step j) includes removing the etchant mask from over the source and drain regions prior to applying conductive straps.

17. A method of fabricating a double gate CMOS device comprising the steps of:

a) providing a silicon on insulator (SOI) substrate with a first silicon layer over a dielectric layer and having an exposed major surface,

b) selectively doping regions of the first silicon layer to accommodate source and drain regions of a first transistor,

c) forming a second dielectric layer over the first silicon layer,

d) forming a second silicon layer over the second dielectric layer,

e) providing an etchant mask over the second silicon layer,

f) patterning the etchant mask to define source, drain, and channel regions of two stacked transistors including the first transistor,

g) etching the first and second silicon layers and the first and second dielectric layers thereby forming source, drain, and channel regions of the two stacked transistors,

h) forming a gate dielectric on sidewalls of the channel regions,

i) depositing gate material over the etchant mask and the gate dielectric,

j) selectively masking and etching the gate material to form a gate on the sidewalls of the channel regions separated from the channel regions by the gate dielectric and the etchant mask, and

k) doping the source and drain regions in the second silicon layer.

18. A method of fabricating a double gate CMOS device comprising the steps of:

a) providing a silicon on insulator (SOI) substrate with a first silicon layer over a dielectric layer and having an exposed major surface,

b) selectively doping regions of the first silicon layer to accommodate source and drain regions of a first transistor,

c) forming a second dielectric layer over the first silicon layer,

d) forming a second silicon layer over the second dielectric layer,

e) providing an etchant mask over the second silicon layer,

f) patterning the etchant mask to define source, drain, and channel regions of two stacked transistors,

g) etching the first and second silicon layers and the first and second dielectric layers thereby forming source, drain, and channel regions of the two stacked transistors,

h) forming a gate dielectric on sidewalls of the channel regions,

i) depositing undoped polysilicon gate material over the etchant mask and the gate dielectric,

j) selectively masking and etching the gate material to form a gate on the sidewalls of the channel regions separated from the channel regions by the gate dielectric and the etchant mask, and

k) doping the gate, source and drain regions in the second silicon layer.

19. The method as defined by claim 18 wherein step k) includes angled shallow ion implantation to limit amorphizing of the source and drain regions.

20. The method as defined by claim 19 and further including the step of annealing the source and drain regions after ion implantation.

21. A double gate MOSFET device comprising:

a) a silicon substrate having a dielectric layer on a major surface,

b) a silicon source region and a silicon drain region with a channel region therebetween extending from the dielectric layer, the channel being a fin with a top surface and two opposing sidewalls,

c) a gate dielectric layer on sidewalls of the channel region and an etchant mask overlying a top of the channel region, and

d) a gate extending over the top and sidewalls of the channel region and electrically isolated therefrom by the gate dielectric and etchant mask.

22. A double gate MOSFET device comprising:

a) a silicon substrate having a dielectric layer on a major surface,

b) a silicon source region and a silicon drain region with a channel region therebetween extending from the dielectric layer,

c) a gate dielectric layer on sidewalls of the channel region and an etchant mask overlying a top of the channel region, the etchant mask being selected from the group consisting of silicon oxide, silicon nitride, and combinations thereof, and

d) a gate extending over the top and sidewalls of the channel region and electrically isolated therefrom by the gate dielectric and etchant mask.

23. The double gate MOSFET device as defined by claim 22 wherein the source region and the drain region are more heavily doped than is the channel region.

24. The double gate MOSFET device as defined by claim 23 wherein the drain region includes a lightly doped region extending to the channel region.

25. The double gate MOSFET device as defined by claim 23 and further including a plurality of channel regions between the source and the drain region.

26. A double gate MOSFET device comprising

a) a silicon substrate having a dielectric layer on a major surface,

b) a silicon source region and a silicon drain region with a plurality of channel regions between the source region and the drain region and extending from the dielectric layer,

c) a gate dielectric layer on sidewalls of the channel region and an etchant mask overlying a top of the channel region, and

d) a gate extending over the top and sidewalls of the channel region and electrically isolated therefrom by the gate dielectric and etchant mask.

27. A double gate CMOS device comprising:

a) a silicon substrate having a dielectric layer on a major surface,

b) a first silicon source region and a first silicon drain region with a first channel region therebetween extending from the dielectric layer,

c) a second silicon source region and a second silicon drain region with a second channel region therebetween overlying the first silicon source region and the first silicon drain region and the first channel region with a dielectric therebetween,

d) a gate dielectric on sidewalls of the channel regions and an etchant mask overlying a top of the second channel region, and

e) a gate extending over the top and sidewalls of the channel regions and electrically isolated therefrom by the gate dielectric and etchant mask.

28. The double gate CMOS device as defined by claim 27 wherein the first source and drain regions are of opposite conductivity type from the second source and drain regions.