Super-self-aligned fabrication process of trench-gate DMOS with overlying device layer

• US 6,413,822 B2
• Filed: 04/22/1999
• Issued: 07/02/2002
• Est. Priority Date: 04/22/1999
• Status: Expired due to Term

• Current Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Inventors: Williams, Richard K., Grabowski, Wayne
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): MALSAWMA, LALRINFAMKIM HMAR
• Application Number:
  US09/296,959
• Publication Number:
  US 20020019099A1
• Time in Patent Office: 1,167 Days
• Field of Search: 438/270, 438/273, 438/294, 438/334, 438/430, 438/431, 438/272, 438/268, 257/331
• US Class Current: 438/270
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A novel super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid-process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.

Claims

1. A method for fabricating a trench MOSFET, comprising providing a body of semiconductor material having a surface;

forming a first mask over the surface, the first mask having an opening where a trench is to be located in the body;

etching the semiconductor material through the opening in the first mask to form a first trench in the body;

forming a second trench in the body;

forming a first oxide layer in the first trench;

introducing a first polysilicon layer into the first trench and the second trench;

introducing a second polysilicon layer over the first polysilicon layer, the second polysilicon layer covering the first polysilicon layer and the first mask;

forming a second mask over the second polysilicon layer, the second mask having an opening over the first trench;

etching the second polysilicon layer through the opening in the second mask, thereby leaving a remaining portion of the second polysilicon layer extending laterally over the surface of the semiconductor body;

etching the first polysilicon layer until an exposed surface of the first polysilicon layer is at a level below the surface of the semiconductor body; and

with the first mask in place, oxidizing an exposed surface of the first polysilicon layer to form a second oxide layer at the top of the first trench, the second oxide layer extending down into the first trench;

removing at least a portion of the first mask; and

depositing a metal layer on a surface of the second oxide layer and the surface of the body.

2. The method of claim 1 comprising:

implanting dopant of a first conductivity type into the remaining portion of the second polysilicon layer;

forming a third mask with an opening over the remaining portion of the second polysilicon layer; and

implanting dopant of a second conductivity type into the second polysilicon layer through the opening in the third mask, thereby to form a PN diode in the remaining portion of second polysilicon layer.

3. The method of claim 2 comprising depositing a metal layer in contact with the surface of the semiconductor body and the remaining portion of the second polysilicon layer.

4. A process comprising:

forming a first mask over a surface of a body of semiconductor material, the first mask having openings where trenches are to be in the body;

etching the semiconductor material through the openings in the first mask to form a first trench and a second trench in the semiconductor body;

forming a first oxide layer in the first and second trenches;

introducing a polysilicon layer into the first and second trenches and overlying the first mask;

forming a second mask over the polysilicon layer, the second mask having an opening over the second trench and a portion of the first mask;

etching the polysilicon layer through the opening in the second mask to expose the portion of the first mask underlying the opening in the second mask and leave a first remaining portion of the polysilicon layer extending laterally under the second mask and a second remaining portion of the polysilicon layer isolated in the second trench;

with the first and second masks in place, oxidizing an exposed surface of the remaining portions of the polysilicon layer to form a second oxide layer at the top of the second trench;

removing the portion of the first mask exposed during the etching through the opening in the second mask; and

depositing a metal layer on a surface of the second oxide layer and the surface of the body.

5. The process of claim 4, wherein oxidizing causes the second oxide layer to extend down into the second trench.

6. The process of claim 4, wherein forming the polysilicon layer comprises:

forming a first layer of polysilicon in the first and second trenches and extending over the first mask;

planarizing the first layer; and

depositing a second layer of polysilicon on the first layer after the planarizing.

7. The process of claim 4, comprising implanting dopants into the first remaining portion of the polysilicon layer to form a PN diode in the first remaining portion of the polysilicon layer.

8. The process of claim 7, wherein depositing the metal layer provides contacts to the surface of the semiconductor body and the first remaining portion of the polysilicon layer.